a2o/dev/verilog/trilib/tri_plat.v

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`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME    : tri_plat.v
// *! DESCRIPTION : Non-scannable pipeline latch
// *!****************************************************************

`include "tri_a2o.vh"

module tri_plat (vd, gd, clk, rst, flush, din, q);
   parameter                      WIDTH = 1;
   parameter                      OFFSET = 0;
   parameter                      INIT = 0;		// will be converted to the least signficant 31 bits of init_v
   parameter                      SYNTHCLONEDLATCH = "";

   inout                          vd;
   inout                          gd;
   input                          clk;
   input                          rst;
   input                          flush;
   input  [OFFSET:OFFSET+WIDTH-1] din;
   output [OFFSET:OFFSET+WIDTH-1] q;

   // tri_plat
   reg  [OFFSET:OFFSET+WIDTH-1]  int_dout;

   (* analysis_not_referenced="true" *)
   wire                          unused;
   assign unused = | {vd, gd};


   always @ (posedge clk)
     begin
 	int_dout <= din;
     end

   assign q = (flush == 1'b1) ? din : int_dout ;

endmodule