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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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//-----------------------------------------------------------------------------------------------------
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// Title: rv_dep.vhdl
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// Desc: Holds the dependency scorecards and second level of itag muxing.
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//
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//-----------------------------------------------------------------------------------------------------
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module rv_dep(
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//------------------------------------------------------------------------------------------------------------
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// IU Control
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//------------------------------------------------------------------------------------------------------------
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input iu_xx_zap,
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input rv0_i0_act,
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input rv0_i1_act,
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//------------------------------------------------------------------------------------------------------------
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// Instruction Sources
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//------------------------------------------------------------------------------------------------------------
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input rv0_instr_i0_vld,
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input rv0_instr_i0_t1_v,
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input rv0_instr_i0_t2_v,
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input rv0_instr_i0_t3_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag,
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input rv0_instr_i0_s1_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag,
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input rv0_instr_i0_s2_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag,
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input rv0_instr_i0_s3_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag,
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input rv0_instr_i1_vld,
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input rv0_instr_i1_t1_v,
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input rv0_instr_i1_t2_v,
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input rv0_instr_i1_t3_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag,
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input rv0_instr_i1_s1_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag,
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input rv0_instr_i1_s2_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag,
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input rv0_instr_i1_s3_v,
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input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag,
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//------------------------------------------------------------------------------------------------------------
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// ITAG Busses
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//------------------------------------------------------------------------------------------------------------
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input fx0_rv_itag_vld,
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input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag,
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input fx1_rv_itag_vld,
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input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag,
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input lq_rv_itag0_vld,
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input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0,
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input lq_rv_itag1_vld,
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input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1,
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input lq_rv_itag2_vld,
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input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2,
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input axu0_rv_itag_vld,
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input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag,
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input axu1_rv_itag_vld,
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input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag,
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input fx0_rv_itag_abort,
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input fx1_rv_itag_abort,
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input lq_rv_itag0_abort,
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input lq_rv_itag1_abort,
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input axu0_rv_itag_abort,
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input axu1_rv_itag_abort,
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//------------------------------------------------------------------------------------------------------------
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// Source Hit Information
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//------------------------------------------------------------------------------------------------------------
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output rv0_instr_i0_s1_dep_hit,
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output rv0_instr_i0_s2_dep_hit,
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output rv0_instr_i0_s3_dep_hit,
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output rv0_instr_i1_s1_dep_hit,
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output rv0_instr_i1_s2_dep_hit,
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output rv0_instr_i1_s3_dep_hit,
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//------------------------------------------------------------------------------------------------------------
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// Pervasive
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//------------------------------------------------------------------------------------------------------------
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inout vdd,
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inout gnd,
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input clk,
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input rst,
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input func_sl_thold_1,
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input sg_1,
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input clkoff_b,
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input act_dis,
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input ccflush_dc,
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input d_mode,
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input delay_lclkr,
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input mpw1_b,
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input mpw2_b,
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input scan_in,
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output scan_out
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);
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//------------------------------------------------------------------------------------------------------------
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// Misc
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//------------------------------------------------------------------------------------------------------------
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wire tiup;
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parameter zero = 0;
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//------------------------------------------------------------------------------------------------------------
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// Input Latches
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//------------------------------------------------------------------------------------------------------------
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wire rv0_sc_act;
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wire [0:6] xx_rv_itag_v_d;
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wire [0:6] xx_rv_itag_v_q;
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wire [0:6] xx_rv_itag_abort_d;
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wire [0:6] xx_rv_itag_abort_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_d;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_q;
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wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_q;
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//------------------------------------------------------------------------------------------------------------
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// GPR PRF Scorecard Signals
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//------------------------------------------------------------------------------------------------------------
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wire i0_target_v;
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wire i1_target_v;
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wire rv0_instr_i0_s1_dep_hit_v;
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wire rv0_instr_i0_s2_dep_hit_v;
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wire rv0_instr_i0_s3_dep_hit_v;
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wire rv0_instr_i1_s1_dep_hit_v;
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wire rv0_instr_i1_s2_dep_hit_v;
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wire rv0_instr_i1_s3_dep_hit_v;
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//------------------------------------------------------------------------------------------------------------
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// Scan
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//------------------------------------------------------------------------------------------------------------
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parameter scorecard_offset = 0;
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parameter xx_rv_itag_v_offset = scorecard_offset + 1;
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parameter xx_rv_itag_abort_offset = xx_rv_itag_v_offset + 7;
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parameter xx_rv_itag_ary0_offset = xx_rv_itag_abort_offset + 7;
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parameter xx_rv_itag_ary1_offset = xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2;
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parameter xx_rv_itag_ary2_offset = xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2;
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parameter xx_rv_itag_ary3_offset = xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2;
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parameter xx_rv_itag_ary4_offset = xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2;
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parameter xx_rv_itag_ary5_offset = xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2;
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parameter xx_rv_itag_ary6_offset = xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2;
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parameter scan_right = xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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wire func_sl_thold_0;
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wire func_sl_thold_0_b;
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wire sg_0;
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wire force_t;
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(* analysis_not_referenced="true" *)
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wire unused;
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assign rv0_sc_act = rv0_i0_act | rv0_i1_act | (|xx_rv_itag_v_q) | (|iu_xx_zap);
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//------------------------------------------------------------------------------------------------------------
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// GPR PRF Scorecard
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//------------------------------------------------------------------------------------------------------------
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assign i0_target_v = rv0_instr_i0_vld & (rv0_instr_i0_t1_v | rv0_instr_i0_t2_v | rv0_instr_i0_t3_v);
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assign i1_target_v = rv0_instr_i1_vld & (rv0_instr_i1_t1_v | rv0_instr_i1_t2_v | rv0_instr_i1_t3_v);
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//num_entries_enc_g => ``GPR_POOL_ENC,
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rv_dep_scard #(.num_entries_g(2 ** (`ITAG_SIZE_ENC - 2)), .itag_width_enc_g(`ITAG_SIZE_ENC - 2) ) sc(
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.iu_xx_zap(iu_xx_zap),
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.rv0_sc_act(rv0_sc_act),
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.ta_v(i0_target_v),
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.ta_itag(rv0_instr_i0_itag[2:`ITAG_SIZE_ENC - 1]),
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.tb_v(i1_target_v),
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.tb_itag(rv0_instr_i1_itag[2:`ITAG_SIZE_ENC - 1]),
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.xx_rv_itag_v(xx_rv_itag_v_q),
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.xx_rv_itag_abort(xx_rv_itag_abort_q),
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.xx_rv_itag_ary0(xx_rv_itag_ary0_q),
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.xx_rv_itag_ary1(xx_rv_itag_ary1_q),
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.xx_rv_itag_ary2(xx_rv_itag_ary2_q),
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.xx_rv_itag_ary3(xx_rv_itag_ary3_q),
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.xx_rv_itag_ary4(xx_rv_itag_ary4_q),
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.xx_rv_itag_ary5(xx_rv_itag_ary5_q),
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.xx_rv_itag_ary6(xx_rv_itag_ary6_q),
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.i0_s1_itag(rv0_instr_i0_s1_itag[2:`ITAG_SIZE_ENC - 1]),
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.i0_s2_itag(rv0_instr_i0_s2_itag[2:`ITAG_SIZE_ENC - 1]),
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.i0_s3_itag(rv0_instr_i0_s3_itag[2:`ITAG_SIZE_ENC - 1]),
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.i1_s1_itag(rv0_instr_i1_s1_itag[2:`ITAG_SIZE_ENC - 1]),
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.i1_s2_itag(rv0_instr_i1_s2_itag[2:`ITAG_SIZE_ENC - 1]),
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.i1_s3_itag(rv0_instr_i1_s3_itag[2:`ITAG_SIZE_ENC - 1]),
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.i0_s1_itag_v(rv0_instr_i0_s1_dep_hit_v),
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.i0_s2_itag_v(rv0_instr_i0_s2_dep_hit_v),
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.i0_s3_itag_v(rv0_instr_i0_s3_dep_hit_v),
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.i1_s1_itag_v(rv0_instr_i1_s1_dep_hit_v),
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.i1_s2_itag_v(rv0_instr_i1_s2_dep_hit_v),
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.i1_s3_itag_v(rv0_instr_i1_s3_dep_hit_v),
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.vdd(vdd),
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.gnd(gnd),
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.clk(clk),
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.rst(rst),
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.chip_b_sl_sg_0_t(sg_0),
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.chip_b_sl_2_thold_0_b(func_sl_thold_0_b),
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.force_t(force_t),
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.d_mode(d_mode),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.scan_in(siv[scorecard_offset]),
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.scan_out(sov[scorecard_offset])
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);
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assign rv0_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit_v & (rv0_instr_i0_s1_v & ~rv0_instr_i0_s1_itag[1]);
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assign rv0_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit_v & (rv0_instr_i0_s2_v & ~rv0_instr_i0_s2_itag[1]);
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assign rv0_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit_v & (rv0_instr_i0_s3_v & ~rv0_instr_i0_s3_itag[1]);
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assign rv0_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_v & (rv0_instr_i1_s1_v & ~rv0_instr_i1_s1_itag[1]);
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assign rv0_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_v & (rv0_instr_i1_s2_v & ~rv0_instr_i1_s2_itag[1]);
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assign rv0_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_v & (rv0_instr_i1_s3_v & ~rv0_instr_i1_s3_itag[1]);
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//------------------------------------------------------------------------------------------------------------
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// Misc
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//------------------------------------------------------------------------------------------------------------
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assign tiup = 1'b1;
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//------------------------------------------------------------------------------------------------------------
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// Release/Abort Busses
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//------------------------------------------------------------------------------------------------------------
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assign xx_rv_itag_v_d[0] = fx0_rv_itag_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[1] = fx1_rv_itag_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[2] = lq_rv_itag0_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[3] = lq_rv_itag1_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[4] = lq_rv_itag2_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[5] = axu0_rv_itag_vld & ~(iu_xx_zap);
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assign xx_rv_itag_v_d[6] = axu1_rv_itag_vld & ~(iu_xx_zap);
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assign xx_rv_itag_ary0_d = fx0_rv_itag[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary1_d = fx1_rv_itag[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary2_d = lq_rv_itag0[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary3_d = lq_rv_itag1[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary4_d = lq_rv_itag2[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary5_d = axu0_rv_itag[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_ary6_d = axu1_rv_itag[2:`ITAG_SIZE_ENC - 1];
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assign xx_rv_itag_abort_d[0] = fx0_rv_itag_abort;
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assign xx_rv_itag_abort_d[1] = fx1_rv_itag_abort;
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assign xx_rv_itag_abort_d[2] = lq_rv_itag0_abort;
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assign xx_rv_itag_abort_d[3] = lq_rv_itag1_abort;
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assign xx_rv_itag_abort_d[4] = 1'b0;
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assign xx_rv_itag_abort_d[5] = axu0_rv_itag_abort;
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assign xx_rv_itag_abort_d[6] = axu1_rv_itag_abort;
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//------------------------------------------------------------------------------------------------------------
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// Latches
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//------------------------------------------------------------------------------------------------------------
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tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_v_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]),
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.scout(sov[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]),
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.din(xx_rv_itag_v_d),
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.dout(xx_rv_itag_v_q)
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);
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tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_abort_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]),
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.scout(sov[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]),
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.din(xx_rv_itag_abort_d),
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.dout(xx_rv_itag_abort_q)
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);
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tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary0_q_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin( siv[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]),
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.scout(sov[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]),
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.din(xx_rv_itag_ary0_d),
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.dout(xx_rv_itag_ary0_q)
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);
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tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary1_q_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin( siv[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]),
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.scout(sov[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]),
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.din(xx_rv_itag_ary1_d),
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.dout(xx_rv_itag_ary1_q)
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);
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tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary2_q_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin( siv[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]),
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.scout(sov[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]),
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.din(xx_rv_itag_ary2_d),
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.dout(xx_rv_itag_ary2_q)
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);
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tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary3_q_reg(
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.vd(vdd),
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.gd(gnd),
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|
.clk(clk),
|
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.rst(rst),
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|
.act(tiup),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.force_t(force_t),
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|
|
.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin( siv[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]),
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.scout(sov[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]),
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|
.din(xx_rv_itag_ary3_d),
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|
.dout(xx_rv_itag_ary3_q)
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|
);
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tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary4_q_reg(
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|
|
.vd(vdd),
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|
|
.gd(gnd),
|
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|
|
|
.clk(clk),
|
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|
|
|
.rst(rst),
|
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|
|
|
.act(tiup),
|
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|
|
|
.thold_b(func_sl_thold_0_b),
|
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|
|
|
.sg(sg_0),
|
|
|
|
|
.force_t(force_t),
|
|
|
|
|
.delay_lclkr(delay_lclkr),
|
|
|
|
|
.mpw1_b(mpw1_b),
|
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|
|
|
.mpw2_b(mpw2_b),
|
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|
|
|
.d_mode(d_mode),
|
|
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|
|
.scin( siv[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]),
|
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|
|
|
.scout(sov[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]),
|
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|
|
.din(xx_rv_itag_ary4_d),
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|
|
.dout(xx_rv_itag_ary4_q)
|
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|
|
);
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|
|
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary5_q_reg(
|
|
|
|
|
.vd(vdd),
|
|
|
|
|
.gd(gnd),
|
|
|
|
|
.clk(clk),
|
|
|
|
|
.rst(rst),
|
|
|
|
|
.act(tiup),
|
|
|
|
|
.thold_b(func_sl_thold_0_b),
|
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|
|
|
.sg(sg_0),
|
|
|
|
|
.force_t(force_t),
|
|
|
|
|
.delay_lclkr(delay_lclkr),
|
|
|
|
|
.mpw1_b(mpw1_b),
|
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|
|
|
.mpw2_b(mpw2_b),
|
|
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|
|
.d_mode(d_mode),
|
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|
|
|
.scin( siv[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]),
|
|
|
|
|
.scout(sov[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]),
|
|
|
|
|
.din(xx_rv_itag_ary5_d),
|
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|
|
|
.dout(xx_rv_itag_ary5_q)
|
|
|
|
|
);
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|
|
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary6_q_reg(
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|
|
|
|
.vd(vdd),
|
|
|
|
|
.gd(gnd),
|
|
|
|
|
.clk(clk),
|
|
|
|
|
.rst(rst),
|
|
|
|
|
.act(tiup),
|
|
|
|
|
.thold_b(func_sl_thold_0_b),
|
|
|
|
|
.sg(sg_0),
|
|
|
|
|
.force_t(force_t),
|
|
|
|
|
.delay_lclkr(delay_lclkr),
|
|
|
|
|
.mpw1_b(mpw1_b),
|
|
|
|
|
.mpw2_b(mpw2_b),
|
|
|
|
|
.d_mode(d_mode),
|
|
|
|
|
.scin( siv[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]),
|
|
|
|
|
.scout(sov[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]),
|
|
|
|
|
.din(xx_rv_itag_ary6_d),
|
|
|
|
|
.dout(xx_rv_itag_ary6_q)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------
|
|
|
|
|
// Scan
|
|
|
|
|
//---------------------------------------------------------------------
|
|
|
|
|
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
|
|
|
|
|
assign scan_out = sov[0];
|
|
|
|
|
|
|
|
|
|
//-----------------------------------------------
|
|
|
|
|
// pervasive
|
|
|
|
|
//-----------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tri_plat #(.WIDTH(2)) perv_1to0_reg(
|
|
|
|
|
.vd(vdd),
|
|
|
|
|
.gd(gnd),
|
|
|
|
|
.clk(clk),
|
|
|
|
|
.rst(rst),
|
|
|
|
|
.flush(ccflush_dc),
|
|
|
|
|
.din({func_sl_thold_1,sg_1}),
|
|
|
|
|
.q({func_sl_thold_0,sg_0})
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tri_lcbor perv_lcbor(
|
|
|
|
|
.clkoff_b(clkoff_b),
|
|
|
|
|
.thold(func_sl_thold_0),
|
|
|
|
|
.sg(sg_0),
|
|
|
|
|
.act_dis(act_dis),
|
|
|
|
|
.force_t(force_t),
|
|
|
|
|
.thold_b(func_sl_thold_0_b)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
//-----------------------------------------------
|
|
|
|
|
// unused signals
|
|
|
|
|
//-----------------------------------------------
|
|
|
|
|
assign unused = rv0_instr_i0_s1_itag[0] | rv0_instr_i0_s2_itag[0] | rv0_instr_i0_s3_itag[0] |
|
|
|
|
|
rv0_instr_i1_s1_itag[0] | rv0_instr_i1_s2_itag[0] | rv0_instr_i1_s3_itag[0] |
|
|
|
|
|
|rv0_instr_i0_itag[0:1] | |rv0_instr_i1_itag[0:1] |
|
|
|
|
|
|fx0_rv_itag[0:1] | |fx1_rv_itag[0:1] | |lq_rv_itag0[0:1] | |lq_rv_itag1[0:1] | |lq_rv_itag2[0:1] | |axu0_rv_itag[0:1] | |axu1_rv_itag[0:1] ;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
