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22 lines
241 B
Verilog
22 lines
241 B
Verilog
2 years ago
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`timescale 1 ps / 1 ps
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module FD (Q, C, D);
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parameter INIT = 1'b0;
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output Q;
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input C, D;
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wire Q;
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reg q_out;
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initial q_out = INIT;
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always @(posedge C)
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q_out <= D;
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assign Q = q_out;
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endmodule
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