1. attempt unit (or sub-unit) synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (equivalent to a CI timing script to catch functional changes that break timing)
* what are the OR steps to do this?
* floorplan - unbounded?
* pins - no placement if no bounds, and relaxed i/o assertions?
* tap cells/power dist/etc. - not needed (account for in estimated wiring?)
* clock tree synthesis - no (assume ideal clocks + fudge)