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630 lines
40 KiB
VHDL
630 lines
40 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity a2o_axi_intr is
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generic (
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 5;
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C_NUM_OF_INTR : integer := 1;
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C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
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C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
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C_IRQ_SENSITIVITY : integer := 1;
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C_IRQ_ACTIVE_STATE : integer := 1
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);
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port (
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_AWPROT : in std_logic_vector(2 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_AWREADY : out std_logic;
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_WREADY : out std_logic;
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_ARPROT : in std_logic_vector(2 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_RREADY : in std_logic;
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irq : out std_logic
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);
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end a2o_axi_intr;
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architecture arch_imp of a2o_axi_intr is
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signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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signal axi_awready : std_logic;
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signal axi_wready : std_logic;
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signal axi_bresp : std_logic_vector(1 downto 0);
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signal axi_bvalid : std_logic;
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signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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signal axi_arready : std_logic;
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signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal axi_rresp : std_logic_vector(1 downto 0);
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signal axi_rvalid : std_logic;
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signal reg_global_intr_en :std_logic_vector(0 downto 0);
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signal reg_intr_en :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal reg_intr_sts :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal reg_intr_ack :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal reg_intr_pending :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal det_intr :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
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signal intr_reg_rden :std_logic;
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signal intr_reg_wren :std_logic;
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signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal intr_counter :std_logic_vector(3 downto 0);
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signal intr_all : std_logic;
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signal intr_ack_all : std_logic;
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signal s_irq : std_logic;
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signal intr_all_ff : std_logic;
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signal intr_ack_all_ff: std_logic;
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signal aw_en : std_logic;
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function or_reduction (vec : in std_logic_vector) return std_logic is
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variable res_v : std_logic := '0';
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begin
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for i in vec'range loop
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res_v := res_v or vec(i);
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end loop;
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return res_v;
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end function;
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begin
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S_AXI_AWREADY <= axi_awready;
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S_AXI_WREADY <= axi_wready;
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S_AXI_BRESP <= axi_bresp;
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S_AXI_BVALID <= axi_bvalid;
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S_AXI_ARREADY <= axi_arready;
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S_AXI_RDATA <= axi_rdata;
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S_AXI_RRESP <= axi_rresp;
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S_AXI_RVALID <= axi_rvalid;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_awready <= '0';
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aw_en <= '1';
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else
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if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
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axi_awready <= '1';
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aw_en <= '0';
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elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
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aw_en <= '1';
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axi_awready <= '0';
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else
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axi_awready <= '0';
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_awaddr <= (others => '0');
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else
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if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
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axi_awaddr <= S_AXI_AWADDR;
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_wready <= '0';
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else
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if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
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axi_wready <= '1';
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else
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axi_wready <= '0';
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end if;
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end if;
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end if;
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end process;
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intr_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
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gen_intr_reg : for i in 0 to (C_NUM_OF_INTR - 1) generate
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begin
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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reg_global_intr_en <= (others => '0');
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else
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if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "000") then
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reg_global_intr_en(0) <= S_AXI_WDATA(0);
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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reg_intr_en(i) <= '0';
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else
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if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "001") then
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reg_intr_en(i) <= S_AXI_WDATA(i);
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
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reg_intr_sts(i) <= '0';
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else
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reg_intr_sts(i) <= det_intr(i);
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
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reg_intr_ack(i) <= '0';
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else
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if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "011") then
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reg_intr_ack(i) <= S_AXI_WDATA(i);
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
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reg_intr_pending(i) <= '0';
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else
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reg_intr_pending(i) <= reg_intr_sts(i) and reg_intr_en(i);
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end if;
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end if;
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end process;
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end generate gen_intr_reg;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_bvalid <= '0';
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axi_bresp <= "00";
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else
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if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
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axi_bvalid <= '1';
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axi_bresp <= "00";
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elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
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axi_bvalid <= '0';
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_arready <= '0';
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axi_araddr <= (others => '1');
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else
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if (axi_arready = '0' and S_AXI_ARVALID = '1') then
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axi_arready <= '1';
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axi_araddr <= S_AXI_ARADDR;
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else
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axi_arready <= '0';
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end if;
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end if;
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end if;
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end process;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_rvalid <= '0';
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axi_rresp <= "00";
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else
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if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
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axi_rvalid <= '1';
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axi_rresp <= "00";
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elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
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axi_rvalid <= '0';
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end if;
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end if;
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end if;
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end process;
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intr_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
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RDATA_INTR_NUM_32: if (C_NUM_OF_INTR=32) generate
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begin
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process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
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variable loc_addr :std_logic_vector(2 downto 0);
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begin
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if S_AXI_ARESETN = '0' then
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reg_data_out <= (others => '0');
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else
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loc_addr := axi_araddr(4 downto 2);
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case loc_addr is
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when "000" =>
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reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
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when "001" =>
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reg_data_out <= reg_intr_en;
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when "010" =>
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reg_data_out <= reg_intr_sts;
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when "011" =>
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reg_data_out <= reg_intr_ack;
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when "100" =>
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reg_data_out <= reg_intr_pending;
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when others =>
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reg_data_out <= (others => '0');
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end case;
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end if;
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end process;
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end generate RDATA_INTR_NUM_32;
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RDATA_INTR_NUM_LESS_32: if (C_NUM_OF_INTR/=32) generate
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begin
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process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
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variable loc_addr :std_logic_vector(2 downto 0);
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variable zero : std_logic_vector (C_S_AXI_DATA_WIDTH-C_NUM_OF_INTR-1 downto 0);
|
||
|
|
begin
|
||
|
|
if S_AXI_ARESETN = '0' then
|
||
|
|
reg_data_out <= (others => '0');
|
||
|
|
zero := (others=>'0');
|
||
|
|
else
|
||
|
|
zero := (others=>'0');
|
||
|
|
loc_addr := axi_araddr(4 downto 2);
|
||
|
|
case loc_addr is
|
||
|
|
when "000" =>
|
||
|
|
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
|
||
|
|
when "001" =>
|
||
|
|
reg_data_out <= zero & reg_intr_en;
|
||
|
|
when "010" =>
|
||
|
|
reg_data_out <= zero & reg_intr_sts;
|
||
|
|
when "011" =>
|
||
|
|
reg_data_out <= zero & reg_intr_ack;
|
||
|
|
when "100" =>
|
||
|
|
reg_data_out <= zero & reg_intr_pending;
|
||
|
|
when others =>
|
||
|
|
reg_data_out <= (others => '0');
|
||
|
|
end case;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
end generate RDATA_INTR_NUM_LESS_32;
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' ) then
|
||
|
|
axi_rdata <= (others => '0');
|
||
|
|
else
|
||
|
|
if (intr_reg_rden = '1') then
|
||
|
|
axi_rdata <= reg_data_out;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0') then
|
||
|
|
intr_counter <= (others => '1');
|
||
|
|
elsif (intr_counter /= x"0") then
|
||
|
|
intr_counter <= std_logic_vector (unsigned(intr_counter) - 1);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0') then
|
||
|
|
intr <= (others => '0');
|
||
|
|
else
|
||
|
|
if (intr_counter = x"a") then
|
||
|
|
intr <= (others => '1');
|
||
|
|
else
|
||
|
|
intr <= (others => '0');
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process (S_AXI_ACLK)
|
||
|
|
variable temp : std_logic;
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then
|
||
|
|
intr_all <= '0';
|
||
|
|
else
|
||
|
|
intr_all <= or_reduction(reg_intr_pending);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process (S_AXI_ACLK)
|
||
|
|
variable temp : std_logic;
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if( S_AXI_ARESETN = '0' or intr_ack_all_ff = '1') then
|
||
|
|
intr_ack_all <= '0';
|
||
|
|
else
|
||
|
|
intr_ack_all <= or_reduction(reg_intr_ack);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0') then
|
||
|
|
intr_all_ff <= '0';
|
||
|
|
intr_ack_all_ff <= '0';
|
||
|
|
else
|
||
|
|
intr_all_ff <= intr_all;
|
||
|
|
intr_ack_all_ff <= intr_ack_all;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
|
||
|
|
gen_intr_detection : for i in 0 to (C_NUM_OF_INTR - 1) generate
|
||
|
|
signal s_irq_lvl: std_logic;
|
||
|
|
begin
|
||
|
|
gen_intr_level_detect: if (C_INTR_SENSITIVITY(i) = '1') generate
|
||
|
|
begin
|
||
|
|
gen_intr_active_high_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate
|
||
|
|
begin
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
det_intr(i) <= '0';
|
||
|
|
else
|
||
|
|
if (intr(i) = '1') then
|
||
|
|
det_intr(i) <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
end generate gen_intr_active_high_detect;
|
||
|
|
|
||
|
|
gen_intr_active_low_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
det_intr(i) <= '0';
|
||
|
|
else
|
||
|
|
if (intr(i) = '0') then
|
||
|
|
det_intr(i) <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
end generate gen_intr_active_low_detect;
|
||
|
|
|
||
|
|
end generate gen_intr_level_detect;
|
||
|
|
|
||
|
|
|
||
|
|
gen_intr_edge_detect: if (C_INTR_SENSITIVITY(i) = '0') generate
|
||
|
|
signal intr_edge : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
|
||
|
|
signal intr_ff : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
|
||
|
|
signal intr_ff2 : std_logic_vector (C_NUM_OF_INTR-1 downto 0);
|
||
|
|
begin
|
||
|
|
gen_intr_rising_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '1') generate
|
||
|
|
begin
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
intr_ff(i) <= '0';
|
||
|
|
intr_ff2(i) <= '0';
|
||
|
|
else
|
||
|
|
intr_ff(i) <= intr(i);
|
||
|
|
intr_ff2(i) <= intr_ff(i);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
intr_edge(i) <= intr_ff(i) and (not intr_ff2(i));
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
det_intr(i) <= '0';
|
||
|
|
elsif (intr_edge(i) = '1') then
|
||
|
|
det_intr(i) <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
end generate gen_intr_rising_edge_detect;
|
||
|
|
|
||
|
|
gen_intr_falling_edge_detect: if (C_INTR_ACTIVE_STATE(i) = '0') generate
|
||
|
|
begin
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
intr_ff(i) <= '0';
|
||
|
|
intr_ff2(i) <= '0';
|
||
|
|
else
|
||
|
|
intr_ff(i) <= intr(i);
|
||
|
|
intr_ff2(i) <= intr_ff(i);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
intr_edge(i) <= intr_ff2(i) and (not intr_ff(i));
|
||
|
|
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
|
||
|
|
det_intr(i) <= '0';
|
||
|
|
elsif (intr_edge(i) = '1') then
|
||
|
|
det_intr(i) <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
end generate gen_intr_falling_edge_detect;
|
||
|
|
|
||
|
|
end generate gen_intr_edge_detect;
|
||
|
|
|
||
|
|
|
||
|
|
gen_irq_level: if (C_IRQ_SENSITIVITY = 1) generate
|
||
|
|
begin
|
||
|
|
irq_level_high: if (C_IRQ_ACTIVE_STATE = 1) generate
|
||
|
|
begin
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
|
||
|
|
s_irq_lvl <= '0';
|
||
|
|
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
|
||
|
|
s_irq_lvl <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
s_irq <= s_irq_lvl;
|
||
|
|
end generate irq_level_high;
|
||
|
|
|
||
|
|
|
||
|
|
irq_level_low: if (C_IRQ_ACTIVE_STATE = 0) generate
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
|
||
|
|
s_irq_lvl <= '1';
|
||
|
|
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
|
||
|
|
s_irq_lvl <= '0';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
s_irq <= s_irq_lvl;
|
||
|
|
end generate irq_level_low;
|
||
|
|
|
||
|
|
end generate gen_irq_level;
|
||
|
|
|
||
|
|
|
||
|
|
gen_irq_edge: if (C_IRQ_SENSITIVITY = 0) generate
|
||
|
|
|
||
|
|
signal s_irq_lvl_ff:std_logic;
|
||
|
|
begin
|
||
|
|
irq_rising_edge: if (C_IRQ_ACTIVE_STATE = 1) generate
|
||
|
|
begin
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
|
||
|
|
s_irq_lvl <= '0';
|
||
|
|
s_irq_lvl_ff <= '0';
|
||
|
|
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
|
||
|
|
s_irq_lvl <= '1';
|
||
|
|
s_irq_lvl_ff <= s_irq_lvl;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
s_irq <= s_irq_lvl and (not s_irq_lvl_ff);
|
||
|
|
end generate irq_rising_edge;
|
||
|
|
|
||
|
|
irq_falling_edge: if (C_IRQ_ACTIVE_STATE = 0) generate
|
||
|
|
begin
|
||
|
|
process( S_AXI_ACLK ) is
|
||
|
|
begin
|
||
|
|
if (rising_edge (S_AXI_ACLK)) then
|
||
|
|
if ( S_AXI_ARESETN = '0' or intr_ack_all = '1') then
|
||
|
|
s_irq_lvl <= '1';
|
||
|
|
s_irq_lvl_ff <= '1';
|
||
|
|
elsif (intr_all = '1' and reg_global_intr_en(0) = '1') then
|
||
|
|
s_irq_lvl <= '0';
|
||
|
|
s_irq_lvl_ff <= s_irq_lvl;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
s_irq <= not (s_irq_lvl_ff and (not s_irq_lvl));
|
||
|
|
end generate irq_falling_edge;
|
||
|
|
|
||
|
|
end generate gen_irq_edge;
|
||
|
|
|
||
|
|
irq <= s_irq;
|
||
|
|
end generate gen_intr_detection;
|
||
|
|
|
||
|
|
end arch_imp;
|