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a2o/dev/sim/coco/Makefile.sweetpea

46 lines
997 B
Makefile

2 years ago
# a2o tb
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim
#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi
#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
SIM_BUILD ?= build_sweetpea
SIM ?= icarus
# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
# icarus
VERILOG_ROOT = ../../verilog
COMPILE_ARGS = -I$(VERILOG_ROOT)/sweetpea -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
# other options
# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./cocotb_icarus.v
TOPLEVEL = cocotb_icarus
# python test
MODULE = tb
# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim
build: clean sim fst
run: sim fst
fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd