openpowerwtf
8 months ago
6 changed files with 1583 additions and 2 deletions
@ -0,0 +1,428 @@
@@ -0,0 +1,428 @@
|
||||
// © IBM Corp. 2022 |
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by |
||||
// the terms below; you may not use the files in this repository except in |
||||
// compliance with the License as modified. |
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 |
||||
// |
||||
// Modified Terms: |
||||
// |
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the |
||||
// License, the "Work" hereby includes implementations of the work of authorship |
||||
// in physical form. |
||||
// |
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses |
||||
// necessary for implementation of the Work that are available from OpenPOWER |
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded |
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions |
||||
// of the EULA. |
||||
// |
||||
// Unless required by applicable law or agreed to in writing, the reference design |
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License |
||||
// for the specific language governing permissions and limitations under the License. |
||||
// |
||||
// Additional rights, including the ability to physically implement a softcore that |
||||
// is compliant with the required sections of the Power ISA Specification, are |
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be |
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. |
||||
|
||||
// A2L2 bridge |
||||
// single req (shared L/S credit) |
||||
// interface to a sim mem[] |
||||
|
||||
`include "tri_a2o.vh" |
||||
|
||||
`timescale 1ns/1ps |
||||
|
||||
module a2l2wb #( |
||||
parameter MEM_MODE = 0, // 0:ext 1:int 2:wb |
||||
parameter MEM_QW = 16384 |
||||
) |
||||
( |
||||
input clk, |
||||
input rst, |
||||
|
||||
input ac_an_req_pwr_token, |
||||
input ac_an_req, |
||||
input [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, |
||||
input [0:5] ac_an_req_ttype, |
||||
input [0:2] ac_an_req_thread, |
||||
input [0:4] ac_an_req_ld_core_tag, |
||||
input [0:2] ac_an_req_ld_xfr_len, |
||||
input ac_an_req_wimg_w, |
||||
input ac_an_req_wimg_i, |
||||
input ac_an_req_wimg_m, |
||||
input ac_an_req_wimg_g, |
||||
input ac_an_req_endian, |
||||
input [0:3] ac_an_req_user_defined, |
||||
input [0:3] ac_an_req_spare_ctrl_a0, |
||||
input ac_an_st_data_pwr_token, |
||||
input [0:31] ac_an_st_byte_enbl, |
||||
input [0:255] ac_an_st_data, |
||||
|
||||
output an_ac_reld_data_vld, |
||||
output [0:4] an_ac_reld_core_tag, |
||||
output [0:127] an_ac_reld_data, |
||||
output [58:59] an_ac_reld_qw, |
||||
output an_ac_reld_ecc_err, |
||||
output an_ac_reld_ecc_err_ue, |
||||
output an_ac_reld_data_coming, |
||||
output an_ac_reld_ditc, |
||||
output an_ac_reld_crit_qw, |
||||
output an_ac_reld_l1_dump, |
||||
output [0:3] an_ac_req_spare_ctrl_a1, |
||||
output [0:`THREADS-1] an_ac_sync_ack, |
||||
|
||||
output an_ac_req_ld_pop, |
||||
output an_ac_req_st_pop, |
||||
output an_ac_req_st_gather, |
||||
|
||||
output [0:`THREADS-1] an_ac_stcx_complete, |
||||
output [0:`THREADS-1] an_ac_stcx_pass, |
||||
output [0:`THREADS-1] an_ac_reservation_vld, |
||||
|
||||
output an_ac_icbi_ack, |
||||
output [0:1] an_ac_icbi_ack_thread, |
||||
output an_ac_back_inv, |
||||
output [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr, |
||||
output [0:4] an_ac_back_inv_target, |
||||
output an_ac_back_inv_local, |
||||
output an_ac_back_inv_lbit, |
||||
output an_ac_back_inv_gs, |
||||
output an_ac_back_inv_ind, |
||||
output [0:7] an_ac_back_inv_lpar_id, |
||||
input ac_an_back_inv_reject, |
||||
input [0:7] ac_an_lpar_id, |
||||
output an_ac_checkstop, |
||||
|
||||
// direct-attach mem |
||||
output [0:31] mem_adr, |
||||
input [0:127] mem_dat, |
||||
output mem_wr_val, |
||||
output [0:15] mem_wr_be, |
||||
output [0:127] mem_wr_dat, |
||||
|
||||
// wishbone |
||||
output wb_stb, |
||||
output wb_cyc, |
||||
output [31:0] wb_adr, |
||||
output wb_we, |
||||
output [3:0] wb_sel, |
||||
output [31:0] wb_datw, |
||||
input wb_ack, |
||||
input [31:0] wb_datr |
||||
); |
||||
|
||||
// unsupported right now |
||||
|
||||
assign an_ac_sync_ack = 0; |
||||
assign an_ac_stcx_complete = 0; |
||||
assign an_ac_stcx_pass = 0; |
||||
assign an_ac_reservation_vld = 0; |
||||
|
||||
assign an_ac_icbi_ack = 0; |
||||
assign an_ac_icbi_ack_thread = 0; |
||||
assign an_ac_back_inv = 0; |
||||
assign an_ac_back_inv_addr = 0; |
||||
assign an_ac_back_inv_target = 0; |
||||
assign an_ac_back_inv_local = 0; |
||||
assign an_ac_back_inv_lbit = 0; |
||||
assign an_ac_back_inv_gs = 0; |
||||
assign an_ac_back_inv_ind = 0; |
||||
assign an_ac_back_inv_lpar_id = 0; |
||||
|
||||
assign an_ac_req_st_gather = 0; |
||||
assign an_ac_req_spare_ctrl_a1 = 0; |
||||
assign an_ac_reld_l1_dump = 0; |
||||
|
||||
wire [0:4] cmdseq_d; |
||||
reg [0:4] cmdseq_q /*verilator public */; |
||||
wire [0:30+`REAL_IFAR_WIDTH] req_d; |
||||
reg [0:30+`REAL_IFAR_WIDTH] req_q; |
||||
wire [0:31+256] std_d; |
||||
reg [0:31+256] std_q; |
||||
reg req_tkn_q; |
||||
reg std_tkn_q; |
||||
wire [0:255] rld_d; |
||||
reg [0:255] rld_q; |
||||
wire [0:1] qw_d; |
||||
reg [0:1] qw_q; |
||||
wire [0:1] mem_qw_d; |
||||
reg [0:1] mem_qw_q; |
||||
wire [0:7] err_d; |
||||
reg [0:7] err_q /*verilator public */; |
||||
|
||||
wire new_req; |
||||
wire req_ld_val; |
||||
wire req_st_val; |
||||
wire req_ieq1; |
||||
wire req_le; |
||||
wire [64-`REAL_IFAR_WIDTH:63] req_adr; |
||||
wire [0:4] req_tag; |
||||
wire [0:2] req_len; |
||||
wire rld_coming; |
||||
wire rld_valid; |
||||
wire rld_done; |
||||
wire [0:1] rld_qw; |
||||
wire idle; |
||||
wire ld_ready; |
||||
wire st_ready; |
||||
wire do_store; |
||||
wire inc_qw; |
||||
|
||||
// FF |
||||
always @(posedge clk) begin |
||||
|
||||
if (rst) begin |
||||
|
||||
cmdseq_q = 'b11111; |
||||
req_q = 0; |
||||
std_q = 0; |
||||
req_tkn_q = 0; |
||||
std_tkn_q = 0; |
||||
qw_q = 0; |
||||
mem_qw_q = 0; |
||||
err_q = 0; |
||||
|
||||
end else begin |
||||
|
||||
cmdseq_q = cmdseq_d; |
||||
req_q = req_d; |
||||
std_q = std_d; |
||||
req_tkn_q = ac_an_req_pwr_token; |
||||
std_tkn_q = ac_an_st_data_pwr_token; |
||||
qw_q = qw_d; |
||||
mem_qw_q = mem_qw_d; |
||||
err_q = err_d; |
||||
|
||||
end |
||||
end |
||||
|
||||
// adr needs to be created for cacheable! |
||||
|
||||
// ext/int mem |
||||
// mem_adr --- (qw-aligned byte address) |
||||
// mem_dat --- |
||||
|
||||
// external memory |
||||
generate if (MEM_MODE == 0) |
||||
assign mem_adr = req_st_val ? {req_adr[32:59], 4'b0000} : //{req_adr[64-`REAL_IFAR_WIDTH:59], 4'b0000} : |
||||
req_ieq1 ? req_adr[32:63] : |
||||
{req_adr[32:57], mem_qw_q, 4'b0000}; //{req_adr[64-`REAL_IFAR_WIDTH:57], mem_qw_q, 4'b0000}; |
||||
endgenerate |
||||
|
||||
// internal memory |
||||
generate if (MEM_MODE == 1) begin |
||||
reg [0:127] mem[MEM_QW]; |
||||
wire [0:127] mem_dat_int; |
||||
|
||||
|
||||
always @(posedge clk) begin |
||||
if (mem_wr_val) begin |
||||
mem[req_adr] = mem_wr_dat; |
||||
end |
||||
end |
||||
assign mem_dat_int = mem[req_adr]; |
||||
end |
||||
endgenerate |
||||
|
||||
|
||||
// clkgate |
||||
// oflow if req_q[0]==1! |
||||
assign new_req = req_tkn_q & ac_an_req; |
||||
assign req_d = new_req ? |
||||
{1'b1, // 0 |
||||
ac_an_req_thread, // 1:3 |
||||
ac_an_req_ttype, // 4:9 |
||||
ac_an_req_ld_core_tag, // 10:14 |
||||
ac_an_req_ra, // 15:56 |
||||
ac_an_req_ld_xfr_len, // 57:59 |
||||
ac_an_req_wimg_w, // 60 |
||||
ac_an_req_wimg_i, // 61 |
||||
ac_an_req_wimg_m, // 62 |
||||
ac_an_req_wimg_g, // 63 |
||||
ac_an_req_endian, // 64 |
||||
ac_an_req_user_defined, // 65:68 |
||||
ac_an_req_spare_ctrl_a0 // 69:72 |
||||
} : |
||||
(rld_done | do_store) ? 0 : req_q; |
||||
|
||||
assign std_d = std_tkn_q ? {ac_an_st_byte_enbl, // 0:31 |
||||
ac_an_st_data // 32:287 |
||||
} : do_store ? 0 : std_q; |
||||
|
||||
// request |
||||
assign req_ld_val = req_q[0] & ( |
||||
(req_q[4:9] == 6'b000000) | // if |
||||
(req_q[4:9] == 6'b001000) | // ld |
||||
(req_q[4:9] == 6'b100010) | // ditc |
||||
(req_q[4:9] == 6'b001001) | // larx |
||||
(req_q[4:9] == 6'b001011) // larx hint |
||||
); |
||||
assign req_ieq1 = req_q[61]; |
||||
assign req_le = req_q[64]; |
||||
|
||||
assign req_st_val = req_q[0] & ( |
||||
(req_q[4:9] == 6'b100000) | // st |
||||
(req_q[4:9] == 6'b101001) // stcx |
||||
); |
||||
|
||||
assign req_tag = req_q[10:14]; |
||||
assign req_adr = req_q[15:15+`REAL_IFAR_WIDTH-1]; |
||||
assign req_len = req_q[57:59]; |
||||
|
||||
// random delay, or future functional stuff |
||||
assign ld_ready = 1; |
||||
assign st_ready = 1; |
||||
|
||||
// b2b |
||||
// coming --- --- |
||||
// valid --- --- --- --- (and qualifiers) |
||||
// data --- --- --- --- (only 1 beat for ieq1) |
||||
|
||||
// vtable -V -b 0 a2l2wb.v |
||||
//tbl cmdseq |
||||
//n cmdseq_q cmdseq_d |
||||
//n | | rld_coming |
||||
//n | req_ld_val | |rld_valid |
||||
//n | |req_st_val | ||do_store |
||||
//n | ||ld_ready | |||rld_done |
||||
//n | |||st_ready | ||||inc_qw |
||||
//n | ||||req_ieq1 | ||||| idle |
||||
//n | ||||| | ||||| | |
||||
//n | ||||| | ||||| | |
||||
//b 01234 ||||| 01234 ||||| | |
||||
//t iiiii iiiii ooooo ooooo o |
||||
//*---------------------------------------------------------------------- |
||||
//* Idle **************************************************************** |
||||
//s 11111 ----- ----- 00000 1 |
||||
//s 11111 00--- 11111 00000 - * ...zzz... |
||||
//s 11111 1---- 00001 00000 - |
||||
//s 11111 -1--- 10000 00000 - |
||||
//* Load **************************************************************** |
||||
//s 00001 --0-- 00001 00000 0 |
||||
//s 00001 --1-- 00010 10000 0 |
||||
//* Reload V0 *********************************************************** * val 0 |
||||
//s 00010 ----- 00011 01001 0 |
||||
//* Reload Nop *********************************************************** * val 1 (not ieq1) |
||||
//s 00011 ----1 00100 00000 0 |
||||
//s 00011 ----0 01000 11001 0 |
||||
//* Reload D0 (I=1) ****************************************************** * dat 0 (ieq1) |
||||
//s 00100 ----- 11111 00010 0 |
||||
//* Reload D0 ************************************************************ * val 2, dat 0 |
||||
//s 01000 ----- 01001 01001 0 |
||||
//* Reload D1 ************************************************************ * val 3, dat 1 |
||||
//s 01001 ----- 01010 01001 0 |
||||
//* Reload D2 ************************************************************ * dat 2 |
||||
//s 01010 ----- 01011 00000 0 |
||||
//* Reload D3 ************************************************************ * dat 3 |
||||
//s 01011 ----- 11111 00010 0 |
||||
//* Store *************************************************************** |
||||
//s 10000 ---0- 10000 00000 0 |
||||
//s 10000 ---1- 11111 00100 0 |
||||
//*---------------------------------------------------------------------- |
||||
//tbl cmdseq |
||||
|
||||
// crit first uses qw pattern instead of +1 |
||||
// valid (d-2) |
||||
assign qw_d = new_req ? 0 : |
||||
inc_qw ? qw_q + 1 : |
||||
qw_q; |
||||
|
||||
assign rld_qw = req_ieq1 ? 2'b00 : qw_q; |
||||
|
||||
// mem address (d-1) |
||||
assign mem_qw_d = rld_qw; |
||||
|
||||
// response |
||||
assign an_ac_reld_ecc_err = 0; |
||||
assign an_ac_reld_ecc_err_ue = 0; |
||||
assign an_ac_reld_ditc = 0; |
||||
|
||||
// loads |
||||
assign an_ac_reld_data_coming = rld_coming; |
||||
assign an_ac_reld_data_vld = rld_valid; |
||||
assign an_ac_reld_core_tag = req_tag; |
||||
assign an_ac_reld_qw = rld_qw; |
||||
assign an_ac_reld_crit_qw = req_ieq1 | (req_adr[58:59] == rld_qw); |
||||
assign an_ac_reld_data = mem_dat; |
||||
assign an_ac_req_ld_pop = rld_done; |
||||
|
||||
// stores |
||||
assign an_ac_req_st_pop = do_store; |
||||
|
||||
// BE, 16B max store |
||||
assign mem_wr_val = do_store; |
||||
assign mem_wr_be = std_q[0:15]; |
||||
assign mem_wr_dat = std_q[32:32+127]; |
||||
|
||||
// misc |
||||
assign err_d = {(new_req & ~idle), 7'b0}; |
||||
assign an_ac_checkstop = err_q != 0; |
||||
|
||||
|
||||
//vtable cmdseq |
||||
assign cmdseq_d[0] = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) + |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_st_val) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & ~st_ready) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign cmdseq_d[1] = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign cmdseq_d[2] = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ieq1) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign cmdseq_d[3] = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign cmdseq_d[4] = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) + |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ld_val) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ~ld_ready) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) + |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign rld_coming = |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1); |
||||
assign rld_valid = |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]); |
||||
assign do_store = |
||||
(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready); |
||||
assign rld_done = |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]); |
||||
assign inc_qw = |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) + |
||||
(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]); |
||||
assign idle = |
||||
(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]); |
||||
//vtable cmdseq |
||||
|
||||
endmodule |
||||
@ -0,0 +1,515 @@
@@ -0,0 +1,515 @@
|
||||
// add ties for all the test junk, etc. so they can be optimized out of model |
||||
|
||||
// © IBM Corp. 2022 |
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by |
||||
// the terms below; you may not use the files in this repository except in |
||||
// compliance with the License as modified. |
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 |
||||
// |
||||
// Modified Terms: |
||||
// |
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the |
||||
// License, the "Work" hereby includes implementations of the work of authorship |
||||
// in physical form. |
||||
// |
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses |
||||
// necessary for implementation of the Work that are available from OpenPOWER |
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded |
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions |
||||
// of the EULA. |
||||
// |
||||
// Unless required by applicable law or agreed to in writing, the reference design |
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License |
||||
// for the specific language governing permissions and limitations under the License. |
||||
// |
||||
// Additional rights, including the ability to physically implement a softcore that |
||||
// is compliant with the required sections of the Power ISA Specification, are |
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be |
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. |
||||
|
||||
`include "tri_a2o.vh" |
||||
|
||||
`timescale 1ns/1ps |
||||
|
||||
module a2owb ( |
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk, |
||||
input scan_in, |
||||
output scan_out, |
||||
|
||||
/* |
||||
// Pervasive clock control |
||||
input an_ac_rtim_sl_thold_8, |
||||
input an_ac_func_sl_thold_8, |
||||
input an_ac_func_nsl_thold_8, |
||||
input an_ac_ary_nsl_thold_8, |
||||
input an_ac_sg_8, |
||||
input an_ac_fce_8, |
||||
input [0:7] an_ac_abst_scan_in, |
||||
|
||||
|
||||
//SCOM Satellite |
||||
input [0:3] an_ac_scom_sat_id, |
||||
input an_ac_scom_dch, |
||||
input an_ac_scom_cch, |
||||
*/ |
||||
output ac_an_scom_dch, |
||||
output ac_an_scom_cch, |
||||
|
||||
// FIR and Error Signals |
||||
output [0:`THREADS-1] ac_an_special_attn, |
||||
output [0:2] ac_an_checkstop, |
||||
output [0:2] ac_an_local_checkstop, |
||||
output [0:2] ac_an_recov_err, |
||||
output ac_an_trace_error, |
||||
output ac_an_livelock_active, |
||||
|
||||
// Perfmon Event Bus |
||||
output [0:4*`THREADS-1] ac_an_event_bus0, |
||||
output [0:4*`THREADS-1] ac_an_event_bus1, |
||||
|
||||
// Power Management |
||||
output [0:`THREADS-1] ac_an_pm_thread_running, |
||||
input [0:`THREADS-1] an_ac_pm_thread_stop, |
||||
input [0:`THREADS-1] an_ac_pm_fetch_halt, |
||||
|
||||
/* |
||||
// Clock, Test, and LCB Controls |
||||
input an_ac_gsd_test_enable_dc, |
||||
input an_ac_gsd_test_acmode_dc, |
||||
input an_ac_ccflush_dc, |
||||
input an_ac_ccenable_dc, |
||||
input an_ac_lbist_en_dc, |
||||
input an_ac_lbist_ip_dc, |
||||
input an_ac_lbist_ac_mode_dc, |
||||
input an_ac_scan_diag_dc, |
||||
input an_ac_scan_dis_dc_b, |
||||
|
||||
//Thold input to clock control macro |
||||
input [0:8] an_ac_scan_type_dc, |
||||
*/ |
||||
|
||||
// Pervasive |
||||
output ac_an_reset_1_request, |
||||
output ac_an_reset_2_request, |
||||
output ac_an_reset_3_request, |
||||
output ac_an_reset_wd_request, |
||||
/* |
||||
input an_ac_lbist_ary_wrt_thru_dc, |
||||
*/ |
||||
input [0:`THREADS-1] an_ac_sleep_en, |
||||
input [0:`THREADS-1] an_ac_ext_interrupt, |
||||
input [0:`THREADS-1] an_ac_crit_interrupt, |
||||
input [0:`THREADS-1] an_ac_perf_interrupt, |
||||
input [0:`THREADS-1] an_ac_hang_pulse, |
||||
input an_ac_tb_update_enable, |
||||
input an_ac_tb_update_pulse, |
||||
/* |
||||
input [0:3] an_ac_chipid_dc, |
||||
input [0:7] an_ac_coreid, |
||||
*/ |
||||
output [0:`THREADS-1] ac_an_machine_check, |
||||
input an_ac_debug_stop, |
||||
output [0:`THREADS-1] ac_an_debug_trigger, |
||||
input [0:`THREADS-1] an_ac_uncond_dbg_event, |
||||
output [0:31] ac_an_debug_bus, |
||||
output ac_an_coretrace_first_valid, |
||||
output ac_an_coretrace_valid, |
||||
output [0:1] ac_an_coretrace_type, |
||||
input an_ac_flh2l2_gate, |
||||
input an_ac_reset_1_complete, |
||||
input an_ac_reset_2_complete, |
||||
input an_ac_reset_3_complete, |
||||
input an_ac_reset_wd_complete, |
||||
output an_ac_checkstop, |
||||
input [0:`THREADS-1] an_ac_external_mchk, |
||||
output ac_an_power_managed, |
||||
output ac_an_rvwinkle_mode, |
||||
|
||||
// direct-attach mem |
||||
output [0:31] mem_adr, |
||||
input [0:127] mem_dat, |
||||
output mem_wr_val, |
||||
output [0:15] mem_wr_be, |
||||
output [0:127] mem_wr_dat, |
||||
|
||||
// wishbone |
||||
output wb_stb, |
||||
output wb_cyc, |
||||
output [31:0] wb_adr, |
||||
output wb_we, |
||||
output [3:0] wb_sel, |
||||
output [31:0] wb_datw, |
||||
input wb_ack, |
||||
input [31:0] wb_datr |
||||
); |
||||
|
||||
wire [0:`THREADS-1] an_ac_stcx_complete /*verilator public */; |
||||
wire [0:`THREADS-1] an_ac_stcx_pass; |
||||
wire an_ac_icbi_ack; |
||||
wire [0:1] an_ac_icbi_ack_thread; |
||||
wire an_ac_back_inv_lbit; |
||||
wire an_ac_back_inv_gs; |
||||
wire an_ac_back_inv_ind; |
||||
wire ac_an_back_inv_reject; |
||||
wire an_ac_reld_data_vld; |
||||
wire an_ac_reld_ecc_err; |
||||
wire an_ac_reld_ecc_err_ue; |
||||
wire an_ac_reld_data_coming; |
||||
wire an_ac_reld_ditc; |
||||
wire an_ac_reld_crit_qw; |
||||
wire an_ac_reld_l1_dump; |
||||
wire an_ac_req_ld_pop; |
||||
wire an_ac_req_st_pop; |
||||
wire an_ac_req_st_gather; |
||||
wire ac_an_req_pwr_token; |
||||
wire ac_an_req /*verilator public */; |
||||
wire ac_an_req_wimg_w; |
||||
wire ac_an_req_wimg_i; |
||||
wire ac_an_req_wimg_m; |
||||
wire ac_an_req_wimg_g; |
||||
wire ac_an_req_endian; |
||||
wire ac_an_st_data_pwr_token; |
||||
wire [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra /*verilator public */; |
||||
wire an_ac_back_inv; |
||||
wire an_ac_back_inv_local; |
||||
wire [0:4] an_ac_back_inv_target; |
||||
wire [0:7] an_ac_back_inv_lpar_id; |
||||
wire [0:7] ac_an_lpar_id; |
||||
wire [0:4] an_ac_reld_core_tag; |
||||
wire [0:127] an_ac_reld_data; |
||||
wire [0:1] an_ac_reld_qw; |
||||
wire [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr; |
||||
wire [0:5] ac_an_req_ttype; |
||||
wire [0:2] ac_an_req_thread; |
||||
wire [0:3] ac_an_req_user_defined; |
||||
wire [0:3] ac_an_req_spare_ctrl_a0; |
||||
wire [0:4] ac_an_req_ld_core_tag; |
||||
wire [0:2] ac_an_req_ld_xfr_len; |
||||
wire [0:31] ac_an_st_byte_enbl; |
||||
wire [0:255] ac_an_st_data; |
||||
wire [0:3] an_ac_req_spare_ctrl_a1; |
||||
wire [0:`THREADS-1] an_ac_sync_ack; |
||||
wire [0:`THREADS-1] an_ac_reservation_vld; |
||||
|
||||
// ties |
||||
wire an_ac_rtim_sl_thold_8; |
||||
wire an_ac_func_sl_thold_8; |
||||
wire an_ac_func_nsl_thold_8; |
||||
wire an_ac_ary_nsl_thold_8; |
||||
wire an_ac_sg_8; |
||||
wire an_ac_fce_8; |
||||
wire [0:7] an_ac_abst_scan_in; |
||||
wire [0:3] an_ac_scom_sat_id; |
||||
wire an_ac_scom_dch; |
||||
wire an_ac_scom_cch; |
||||
wire an_ac_gsd_test_enable_dc; |
||||
wire an_ac_gsd_test_acmode_dc; |
||||
wire an_ac_ccflush_dc; |
||||
wire an_ac_ccenable_dc; |
||||
wire an_ac_lbist_en_dc; |
||||
wire an_ac_lbist_ip_dc; |
||||
wire an_ac_lbist_ac_mode_dc; |
||||
wire an_ac_scan_diag_dc; |
||||
wire an_ac_scan_dis_dc_b; |
||||
wire [0:8] an_ac_scan_type_dc; |
||||
wire an_ac_lbist_ary_wrt_thru_dc; |
||||
wire [0:3] an_ac_chipid_dc; |
||||
wire [0:7] an_ac_coreid; |
||||
|
||||
assign an_ac_chipid_dc = 4'h0; |
||||
assign an_ac_coreid = 8'h0; |
||||
|
||||
// Pervasive clock control |
||||
assign an_ac_rtim_sl_thold_8 = 0; |
||||
assign an_ac_func_sl_thold_8 = 0; |
||||
assign an_ac_func_nsl_thold_8 = 0; |
||||
assign an_ac_ary_nsl_thold_8 = 0; |
||||
assign an_ac_sg_8 = 0; |
||||
assign an_ac_fce_8 = 0; |
||||
assign an_ac_abst_scan_in = 8'h00; |
||||
|
||||
// SCOM |
||||
assign an_ac_scom_sat_id = 4'h0; |
||||
assign an_ac_scom_dch = 0; |
||||
assign an_ac_scom_cch = 0; |
||||
|
||||
// Clock, Test, and LCB Controls |
||||
assign an_ac_gsd_test_enable_dc = 0; |
||||
assign an_ac_gsd_test_acmode_dc = 0; |
||||
assign an_ac_ccflush_dc = 0; |
||||
assign an_ac_ccenable_dc = 0; |
||||
assign an_ac_lbist_en_dc = 0; |
||||
assign an_ac_lbist_ip_dc = 0; |
||||
assign an_ac_lbist_ac_mode_dc = 0; |
||||
assign an_ac_scan_diag_dc = 0; |
||||
assign an_ac_scan_dis_dc_b = 0; |
||||
|
||||
assign an_ac_scan_type_dc = 9'h000; |
||||
assign an_ac_lbist_ary_wrt_thru_dc = 0; |
||||
|
||||
|
||||
c c0( |
||||
.nclk(nclk), |
||||
.scan_in(scan_in), |
||||
.scan_out(scan_out), |
||||
|
||||
.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8), |
||||
.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8), |
||||
.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8), |
||||
.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8), |
||||
.an_ac_sg_8(an_ac_sg_8), |
||||
.an_ac_fce_8(an_ac_fce_8), |
||||
.an_ac_abst_scan_in(an_ac_abst_scan_in), |
||||
|
||||
.an_ac_stcx_complete(an_ac_stcx_complete[0]), |
||||
.an_ac_stcx_pass(an_ac_stcx_pass[0]), |
||||
.an_ac_reservation_vld(an_ac_reservation_vld[0]), |
||||
|
||||
.an_ac_icbi_ack(an_ac_icbi_ack), |
||||
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), |
||||
.an_ac_sync_ack(an_ac_sync_ack[0]), |
||||
|
||||
.an_ac_back_inv(an_ac_back_inv), |
||||
.an_ac_back_inv_addr(an_ac_back_inv_addr), |
||||
.an_ac_back_inv_target(an_ac_back_inv_target), |
||||
.an_ac_back_inv_local(an_ac_back_inv_local), |
||||
.an_ac_back_inv_lbit(an_ac_back_inv_lbit), |
||||
.an_ac_back_inv_gs(an_ac_back_inv_gs), |
||||
.an_ac_back_inv_ind(an_ac_back_inv_ind), |
||||
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), |
||||
.ac_an_back_inv_reject(ac_an_back_inv_reject), |
||||
.ac_an_lpar_id(ac_an_lpar_id), |
||||
|
||||
.an_ac_reld_data_vld(an_ac_reld_data_vld), |
||||
.an_ac_reld_core_tag(an_ac_reld_core_tag), |
||||
.an_ac_reld_data(an_ac_reld_data), |
||||
.an_ac_reld_qw(an_ac_reld_qw), |
||||
.an_ac_reld_ecc_err(an_ac_reld_ecc_err), |
||||
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), |
||||
.an_ac_reld_data_coming(an_ac_reld_data_coming), |
||||
.an_ac_reld_ditc(an_ac_reld_ditc), |
||||
.an_ac_reld_crit_qw(an_ac_reld_crit_qw), |
||||
.an_ac_reld_l1_dump(an_ac_reld_l1_dump), |
||||
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), |
||||
|
||||
.an_ac_flh2l2_gate(an_ac_flh2l2_gate), |
||||
.an_ac_req_ld_pop(an_ac_req_ld_pop), |
||||
.an_ac_req_st_pop(an_ac_req_st_pop), |
||||
.an_ac_req_st_gather(an_ac_req_st_gather), |
||||
.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), |
||||
|
||||
.an_ac_scom_sat_id(an_ac_scom_sat_id), |
||||
.an_ac_scom_dch(an_ac_scom_dch), |
||||
.an_ac_scom_cch(an_ac_scom_cch), |
||||
.ac_an_scom_dch(ac_an_scom_dch), |
||||
.ac_an_scom_cch(ac_an_scom_cch), |
||||
|
||||
.ac_an_special_attn(ac_an_special_attn), |
||||
.ac_an_checkstop(ac_an_checkstop), |
||||
.ac_an_local_checkstop(ac_an_local_checkstop), |
||||
.ac_an_recov_err(ac_an_recov_err), |
||||
.ac_an_trace_error(ac_an_trace_error), |
||||
.ac_an_livelock_active(ac_an_livelock_active), |
||||
.an_ac_checkstop(an_ac_checkstop), |
||||
.an_ac_external_mchk(an_ac_external_mchk), |
||||
|
||||
.ac_an_event_bus0(ac_an_event_bus0), |
||||
|
||||
.an_ac_reset_1_complete(an_ac_reset_1_complete), |
||||
.an_ac_reset_2_complete(an_ac_reset_2_complete), |
||||
.an_ac_reset_3_complete(an_ac_reset_3_complete), |
||||
.an_ac_reset_wd_complete(an_ac_reset_wd_complete), |
||||
|
||||
.ac_an_pm_thread_running(ac_an_pm_thread_running), |
||||
.an_ac_pm_thread_stop(an_ac_pm_thread_stop), |
||||
.ac_an_power_managed(ac_an_power_managed), |
||||
.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), |
||||
|
||||
.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc), |
||||
.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), |
||||
.an_ac_ccflush_dc(an_ac_ccflush_dc), |
||||
.an_ac_ccenable_dc(an_ac_ccenable_dc), |
||||
.an_ac_lbist_en_dc(an_ac_lbist_en_dc), |
||||
.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc), |
||||
.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc), |
||||
.an_ac_scan_diag_dc(an_ac_scan_diag_dc), |
||||
.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), |
||||
.an_ac_scan_type_dc(an_ac_scan_type_dc), |
||||
.ac_an_reset_1_request(ac_an_reset_1_request), |
||||
.ac_an_reset_2_request(ac_an_reset_2_request), |
||||
.ac_an_reset_3_request(ac_an_reset_3_request), |
||||
.ac_an_reset_wd_request(ac_an_reset_wd_request), |
||||
.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), |
||||
.an_ac_sleep_en(an_ac_sleep_en), |
||||
.an_ac_ext_interrupt(an_ac_ext_interrupt), |
||||
.an_ac_crit_interrupt(an_ac_crit_interrupt), |
||||
.an_ac_perf_interrupt(an_ac_perf_interrupt), |
||||
.an_ac_hang_pulse(an_ac_hang_pulse), |
||||
.an_ac_tb_update_enable(an_ac_tb_update_enable), |
||||
.an_ac_tb_update_pulse(an_ac_tb_update_pulse), |
||||
.an_ac_chipid_dc(an_ac_chipid_dc), |
||||
.an_ac_coreid(an_ac_coreid), |
||||
.ac_an_machine_check(ac_an_machine_check), |
||||
.an_ac_debug_stop(an_ac_debug_stop), |
||||
.ac_an_debug_trigger(ac_an_debug_trigger), |
||||
.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), |
||||
|
||||
.ac_an_req_pwr_token(ac_an_req_pwr_token), |
||||
.ac_an_req(ac_an_req), |
||||
.ac_an_req_ra(ac_an_req_ra), |
||||
.ac_an_req_ttype(ac_an_req_ttype), |
||||
.ac_an_req_thread(ac_an_req_thread), |
||||
.ac_an_req_wimg_w(ac_an_req_wimg_w), |
||||
.ac_an_req_wimg_i(ac_an_req_wimg_i), |
||||
.ac_an_req_wimg_m(ac_an_req_wimg_m), |
||||
.ac_an_req_wimg_g(ac_an_req_wimg_g), |
||||
.ac_an_req_user_defined(ac_an_req_user_defined), |
||||
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), |
||||
.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), |
||||
.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), |
||||
.ac_an_st_byte_enbl(ac_an_st_byte_enbl), |
||||
.ac_an_st_data(ac_an_st_data), |
||||
.ac_an_req_endian(ac_an_req_endian), |
||||
.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token) |
||||
); |
||||
|
||||
a2l2wb n0( |
||||
.clk(clk_1x), |
||||
.rst(rst), |
||||
|
||||
// request |
||||
.ac_an_req_pwr_token(ac_an_req_pwr_token), |
||||
.ac_an_req(ac_an_req), |
||||
.ac_an_req_ra(ac_an_req_ra), |
||||
.ac_an_req_ttype(ac_an_req_ttype), |
||||
.ac_an_req_thread(ac_an_req_thread), |
||||
.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), |
||||
.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), |
||||
.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token), |
||||
.ac_an_st_byte_enbl(ac_an_st_byte_enbl), |
||||
.ac_an_st_data(ac_an_st_data), |
||||
.ac_an_req_wimg_w(ac_an_req_wimg_w), |
||||
.ac_an_req_wimg_i(ac_an_req_wimg_i), |
||||
.ac_an_req_wimg_m(ac_an_req_wimg_m), |
||||
.ac_an_req_wimg_g(ac_an_req_wimg_g), |
||||
.ac_an_req_endian(ac_an_req_endian), |
||||
.ac_an_req_user_defined(ac_an_req_user_defined), |
||||
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), |
||||
|
||||
// reload |
||||
.an_ac_reld_data_vld(an_ac_reld_data_vld), |
||||
.an_ac_reld_core_tag(an_ac_reld_core_tag), |
||||
.an_ac_reld_data(an_ac_reld_data), |
||||
.an_ac_reld_qw(an_ac_reld_qw), |
||||
.an_ac_reld_ecc_err(an_ac_reld_ecc_err), |
||||
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), |
||||
.an_ac_reld_data_coming(an_ac_reld_data_coming), |
||||
.an_ac_reld_ditc(an_ac_reld_ditc), |
||||
.an_ac_reld_crit_qw(an_ac_reld_crit_qw), |
||||
.an_ac_reld_l1_dump(an_ac_reld_l1_dump), |
||||
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), |
||||
|
||||
// larx/stcx |
||||
.an_ac_stcx_complete(an_ac_stcx_complete), |
||||
.an_ac_stcx_pass(an_ac_stcx_pass), |
||||
.an_ac_reservation_vld(an_ac_reservation_vld), |
||||
|
||||
// icbi |
||||
.an_ac_icbi_ack(an_ac_icbi_ack), |
||||
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), |
||||
|
||||
// back invalidate |
||||
.an_ac_back_inv(an_ac_back_inv), |
||||
.an_ac_back_inv_addr(an_ac_back_inv_addr), |
||||
.an_ac_back_inv_target(an_ac_back_inv_target), |
||||
.an_ac_back_inv_local(an_ac_back_inv_local), |
||||
.an_ac_back_inv_lbit(an_ac_back_inv_lbit), |
||||
.an_ac_back_inv_gs(an_ac_back_inv_gs), |
||||
.an_ac_back_inv_ind(an_ac_back_inv_ind), |
||||
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), |
||||
.ac_an_back_inv_reject(ac_an_back_inv_reject), |
||||
.ac_an_lpar_id(ac_an_lpar_id), |
||||
|
||||
// credits |
||||
.an_ac_req_ld_pop(an_ac_req_ld_pop), |
||||
.an_ac_req_st_pop(an_ac_req_st_pop), |
||||
.an_ac_req_st_gather(an_ac_req_st_gather), |
||||
.an_ac_sync_ack(an_ac_sync_ack), |
||||
//.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), |
||||
|
||||
// misc |
||||
//.an_ac_flh2l2_gate(an_ac_flh2l2_gate), |
||||
//.an_ac_reset_1_complete(an_ac_reset_1_complete), |
||||
//.an_ac_reset_2_complete(an_ac_reset_2_complete), |
||||
//.an_ac_reset_3_complete(an_ac_reset_3_complete), |
||||
//.an_ac_reset_wd_complete(an_ac_reset_wd_complete), |
||||
//.an_ac_sleep_en(an_ac_sleep_en), |
||||
//.an_ac_ext_interrupt(an_ac_ext_interrupt), |
||||
//.an_ac_crit_interrupt(an_ac_crit_interrupt), |
||||
//.an_ac_perf_interrupt(an_ac_perf_interrupt), |
||||
//.an_ac_hang_pulse(an_ac_hang_pulse), |
||||
//.an_ac_tb_update_enable(an_ac_tb_update_enable), |
||||
//.an_ac_tb_update_pulse(an_ac_tb_update_pulse), |
||||
//.an_ac_chipid_dc(an_ac_chipid_dc), |
||||
//.an_ac_coreid(an_ac_coreid), |
||||
//.an_ac_debug_stop(an_ac_debug_stop), |
||||
//.ac_an_debug_trigger(ac_an_debug_trigger), |
||||
//.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), |
||||
|
||||
// scom |
||||
//.an_ac_scom_sat_id(an_ac_scom_sat_id), |
||||
//.an_ac_scom_dch(an_ac_scom_dch), |
||||
//.an_ac_scom_cch(an_ac_scom_cch), |
||||
//.ac_an_scom_dch(ac_an_scom_dch), |
||||
//.ac_an_scom_cch(ac_an_scom_cch), |
||||
|
||||
// errors |
||||
//.ac_an_special_attn(ac_an_special_attn), |
||||
//.ac_an_checkstop(ac_an_checkstop), |
||||
//.ac_an_local_checkstop(ac_an_local_checkstop), |
||||
//.ac_an_recov_err(ac_an_recov_err), |
||||
//.ac_an_trace_error(ac_an_trace_error), |
||||
//.ac_an_livelock_active(ac_an_livelock_active), |
||||
.an_ac_checkstop(an_ac_checkstop), |
||||
//.an_ac_external_mchk(an_ac_external_mchk), |
||||
//.ac_an_machine_check(ac_an_machine_check), |
||||
|
||||
// perfmon |
||||
//.ac_an_event_bus0(ac_an_event_bus0), |
||||
//.ac_an_event_bus1(ac_an_event_bus1), |
||||
|
||||
// power |
||||
//.ac_an_pm_thread_running(ac_an_pm_thread_running), |
||||
//.an_ac_pm_thread_stop(an_ac_pm_thread_stop), |
||||
//.ac_an_power_managed(ac_an_power_managed), |
||||
//.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode) |
||||
// direct-attach mem |
||||
.mem_adr(mem_adr), |
||||
.mem_dat(mem_dat), |
||||
.mem_wr_be(mem_wr_be), |
||||
.mem_wr_val(mem_wr_val), |
||||
|
||||
.mem_wr_dat(mem_wr_dat), |
||||
|
||||
// wishbone |
||||
.wb_stb(wb_stb), |
||||
.wb_cyc(wb_cyc), |
||||
.wb_adr(wb_adr), |
||||
.wb_we(wb_we), |
||||
.wb_ack(wb_ack), |
||||
.wb_sel(wb_sel), |
||||
.wb_datr(wb_datr), |
||||
.wb_datw(wb_datw) |
||||
|
||||
); |
||||
|
||||
wire clk_1x, clk_2x, clk_4x, rst; |
||||
|
||||
assign clk_1x = nclk[0]; |
||||
assign clk_2x = nclk[2]; |
||||
assign clk_4x = nclk[3]; |
||||
assign rst = nclk[1]; |
||||
|
||||
endmodule |
||||
@ -0,0 +1,194 @@
@@ -0,0 +1,194 @@
|
||||
// © IBM Corp. 2020 |
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by |
||||
// the terms below; you may not use the files in this repository except in |
||||
// compliance with the License as modified. |
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 |
||||
// |
||||
// Modified Terms: |
||||
// |
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the |
||||
// License, the "Work" hereby includes implementations of the work of authorship |
||||
// in physical form. |
||||
// |
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses |
||||
// necessary for implementation of the Work that are available from OpenPOWER |
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded |
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions |
||||
// of the EULA. |
||||
// |
||||
// Unless required by applicable law or agreed to in writing, the reference design |
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License |
||||
// for the specific language governing permissions and limitations under the License. |
||||
// |
||||
// Additional rights, including the ability to physically implement a softcore that |
||||
// is compliant with the required sections of the Power ISA Specification, are |
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be |
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. |
||||
|
||||
// Transaction limiting |
||||
// LOAD_CREDITS=1, STORE_CREDITS=1, XUCR0[52]=1 |
||||
|
||||
`ifndef _tri_a2o_vh_ |
||||
`define _tri_a2o_vh_ |
||||
|
||||
`include "tri.vh" |
||||
|
||||
// Use this line for 1 thread. Comment out for 2 thread design. |
||||
`define THREADS1 |
||||
|
||||
`define gpr_t 3'b000 |
||||
`define cr_t 3'b001 |
||||
`define lr_t 3'b010 |
||||
`define ctr_t 3'b011 |
||||
`define xer_t 3'b100 |
||||
`define spr_t 3'b101 |
||||
`define axu0_t 3'b110 |
||||
`define axu1_t 3'b111 |
||||
|
||||
`ifdef THREADS1 |
||||
`define THREADS 1 |
||||
`define THREAD_POOL_ENC 0 |
||||
`define THREADS_POOL_ENC 0 |
||||
`else |
||||
`define THREADS 2 |
||||
`define THREAD_POOL_ENC 1 |
||||
`define THREADS_POOL_ENC 1 |
||||
`endif |
||||
`define EFF_IFAR_ARCH 62 |
||||
`define EFF_IFAR_WIDTH 20 |
||||
`define EFF_IFAR 20 |
||||
`define FPR_POOL_ENC 6 |
||||
`define REGMODE 6 |
||||
`define FPR_POOL 64 |
||||
`define REAL_IFAR_WIDTH 42 |
||||
`define EMQ_ENTRIES 4 |
||||
`define GPR_WIDTH 64 |
||||
`define ITAG_SIZE_ENC 7 |
||||
`define CPL_Q_DEPTH 32 |
||||
`define CPL_Q_DEPTH_ENC 6 |
||||
`define GPR_WIDTH_ENC 6 |
||||
`define GPR_POOL_ENC 6 |
||||
`define GPR_POOL 64 |
||||
`define GPR_UCODE_POOL 4 |
||||
`define CR_POOL_ENC 5 |
||||
`define CR_POOL 24 |
||||
`define CR_UCODE_POOL 1 |
||||
`define BR_POOL_ENC 3 |
||||
`define BR_POOL 8 |
||||
`define LR_POOL_ENC 3 |
||||
`define LR_POOL 8 |
||||
`define LR_UCODE_POOL 0 |
||||
`define CTR_POOL_ENC 3 |
||||
`define CTR_POOL 8 |
||||
`define CTR_UCODE_POOL 0 |
||||
`define XER_POOL_ENC 4 |
||||
`define XER_POOL 12 |
||||
`define XER_UCODE_POOL 0 |
||||
`define LDSTQ_ENTRIES 16 |
||||
`define LDSTQ_ENTRIES_ENC 4 |
||||
`define STQ_ENTRIES 12 |
||||
`define STQ_ENTRIES_ENC 4 |
||||
`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from |
||||
`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported |
||||
`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ |
||||
`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE |
||||
`define LMQ_ENTRIES 8 |
||||
`define LMQ_ENTRIES_ENC 3 |
||||
`define LGQ_ENTRIES 8 |
||||
`define AXU_SPARE_ENC 3 |
||||
`define RV_FX0_ENTRIES 12 |
||||
`define RV_FX1_ENTRIES 12 |
||||
`define RV_LQ_ENTRIES 16 |
||||
`define RV_AXU0_ENTRIES 12 |
||||
`define RV_AXU1_ENTRIES 0 |
||||
`define RV_FX0_ENTRIES_ENC 4 |
||||
`define RV_FX1_ENTRIES_ENC 4 |
||||
`define RV_LQ_ENTRIES_ENC 4 |
||||
`define RV_AXU0_ENTRIES_ENC 4 |
||||
`define RV_AXU1_ENTRIES_ENC 1 |
||||
`define UCODE_ENTRIES 8 |
||||
`define UCODE_ENTRIES_ENC 3 |
||||
`define FXU1_ENABLE 1 |
||||
`define TYPE_WIDTH 3 |
||||
`define IBUFF_INSTR_WIDTH 70 |
||||
`define IBUFF_IFAR_WIDTH 20 |
||||
`define IBUFF_DEPTH 16 |
||||
`define PF_IAR_BITS 12 // number of IAR bits used by prefetch |
||||
`define FXU0_PIPE_START 1 |
||||
`define FXU0_PIPE_END 8 |
||||
`define FXU1_PIPE_START 1 |
||||
`define FXU1_PIPE_END 5 |
||||
`define LQ_LOAD_PIPE_START 4 |
||||
`define LQ_LOAD_PIPE_END 8 |
||||
`define LQ_REL_PIPE_START 2 |
||||
`define LQ_REL_PIPE_END 4 |
||||
`define LOAD_CREDITS 1 |
||||
`define STORE_CREDITS 1 |
||||
`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size |
||||
`define MMQ_ENTRIES 2 // MMU Queue Size |
||||
`define CR_WIDTH 4 |
||||
`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch |
||||
`define PF_IFAR_WIDTH 12 |
||||
`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch |
||||
`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) |
||||
`define PFETCH_Q_SIZE 8 // number of entries |
||||
`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) |
||||
`define XER_WIDTH 10 |
||||
|
||||
//wtf: change for verilatorsim - didnt help |
||||
//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT |
||||
`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT |
||||
//`define INIT_IUCR0 16'h0000 // BP disabled |
||||
`define INIT_IUCR0 16'h00FA // BP enabled |
||||
|
||||
|
||||
`define INIT_MASK 2'b10 |
||||
`define RELQ_INCLUDE 0 // Reload Queue Included |
||||
|
||||
`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 |
||||
|
||||
//wtf: add completion stuff |
||||
/* |
||||
assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39]; |
||||
assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47]; |
||||
assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55]; |
||||
assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63]; |
||||
*/ |
||||
`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 |
||||
//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 |
||||
/* |
||||
assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47]; |
||||
assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55]; |
||||
*/ |
||||
`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 |
||||
//`define INIT_CPCR1 32'h00010100 // 1/1 |
||||
|
||||
`define INIT_XUCR0 32'h00000C60 // 52:single-credit LS |
||||
|
||||
// IERAT boot config entry values |
||||
`define IERAT_BCFG_EPN_0TO15 0 |
||||
`define IERAT_BCFG_EPN_16TO31 0 |
||||
`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G |
||||
`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G |
||||
`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff |
||||
`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G |
||||
`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G |
||||
`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page |
||||
`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page |
||||
`define IERAT_BCFG_ATTR 0 // u0-u3, endian |
||||
|
||||
// DERAT boot config entry values |
||||
`define DERAT_BCFG_EPN_0TO15 0 |
||||
`define DERAT_BCFG_EPN_16TO31 0 |
||||
`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G |
||||
`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G |
||||
`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff |
||||
`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G |
||||
`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G |
||||
`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page |
||||
`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page |
||||
`define DERAT_BCFG_ATTR 0 // u0-u3, endian |
||||
|
||||
// Do NOT add any defines below this line |
||||
`endif //_tri_a2o_vh_ |
||||
@ -0,0 +1,427 @@
@@ -0,0 +1,427 @@
|
||||
#!/usr/bin/python3 |
||||
# |
||||
# Parse table comments and create equations. |
||||
|
||||
from optparse import OptionParser |
||||
import re |
||||
from shutil import copyfile |
||||
|
||||
#-------------------------------------------------------------------------------------------------- |
||||
# Initialize |
||||
|
||||
TYPE_INPUT = 0 |
||||
TYPE_OUTPUT = 1 |
||||
TYPE_SKIP = 99 |
||||
|
||||
lines = [] |
||||
tableMatches = [] |
||||
tableNames = [] |
||||
tableLines = [] |
||||
tables = {} |
||||
|
||||
failOnError = True |
||||
inFile = 'test.vhdl' |
||||
outFileExt = 'vtable' |
||||
overwrite = True |
||||
backupExt = 'orig' |
||||
backup = True |
||||
noisy = False |
||||
quiet = False |
||||
verilog = False |
||||
|
||||
#-------------------------------------------------------------------------------------------------- |
||||
# Handle command line |
||||
|
||||
usage = 'vtable [options] inFile' |
||||
|
||||
parser = OptionParser(usage) |
||||
parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt) |
||||
parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite)) |
||||
parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup)) |
||||
parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet)) |
||||
parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy)) |
||||
parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog)) |
||||
|
||||
options, args = parser.parse_args() |
||||
|
||||
if len(args) != 1: |
||||
parser.error(usage) |
||||
quit(-1) |
||||
else: |
||||
inFile = args[0] |
||||
|
||||
if options.overwrite == '0': |
||||
overwrite = False |
||||
elif options.overwrite == '1': |
||||
overwrite == True |
||||
if options.outFile is not None: |
||||
parser.error('Can\'t specify outfile and overrite!') |
||||
quit(-1) |
||||
elif options.overwrite is not None: |
||||
parser.error('overwrite: 0|1') |
||||
quit(-1) |
||||
|
||||
if options.quiet is not None: |
||||
quiet = True |
||||
|
||||
if options.noisy is not None: |
||||
noisy = True |
||||
|
||||
if options.verilog is not None: |
||||
verilog = True |
||||
|
||||
if options.backup == '0': |
||||
backup = False |
||||
elif options.backup == '1': |
||||
backup == True |
||||
elif options.backup is not None: |
||||
parser.error('backup: 0|1') |
||||
quit(-1) |
||||
|
||||
if options.outFile is not None: |
||||
outFile = options.outFile |
||||
elif overwrite: |
||||
outFile = inFile |
||||
else: |
||||
outFile = inFile + '.' + outFileExt |
||||
|
||||
backupFile = inFile + '.' + backupExt |
||||
|
||||
#-------------------------------------------------------------------------------------------------- |
||||
# Objects |
||||
|
||||
class Signal: |
||||
|
||||
def __init__(self, name, type): |
||||
self.name = name; |
||||
self.type = type; |
||||
|
||||
class Table: |
||||
|
||||
def __init__(self, name): |
||||
self.name = name |
||||
self.source = [] |
||||
self.signals = {} |
||||
self.signalsByCol = {} |
||||
self.typesByCol = {} |
||||
self.specs = [] # list of specsByCol |
||||
self.equations = [] |
||||
self.added = False |
||||
|
||||
def validate(self): |
||||
# check that all signals have a good type |
||||
for col in self.signalsByCol: |
||||
if col not in self.typesByCol: |
||||
error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col]) |
||||
elif self.typesByCol[col] == None: |
||||
error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col])) |
||||
|
||||
def makeRTL(self, form=None): |
||||
outputsByCol = {} |
||||
|
||||
|
||||
#for col,type in self.typesByCol.items(): |
||||
for col in sorted(self.typesByCol): |
||||
type = self.typesByCol[col] |
||||
if type == TYPE_OUTPUT: |
||||
if col in self.signalsByCol: |
||||
outputsByCol[col] = self.signalsByCol[col] |
||||
else: |
||||
print(self.signalsByCol) |
||||
print(self.typesByCol) |
||||
error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists') |
||||
|
||||
#for sigCol,sig in outputsByCol.items(): |
||||
for sigCol in sorted(outputsByCol): |
||||
sig = outputsByCol[sigCol] |
||||
if not verilog: |
||||
line = sig + ' <= ' |
||||
else: |
||||
line = 'assign ' + sig + ' = ' |
||||
nonzero = False |
||||
for specsByCol in self.specs: |
||||
terms = [] |
||||
if sigCol not in specsByCol: |
||||
#error('* Output ' + sig + ' has no specified value for column ' + str(col)) |
||||
1 # no error, can be dontcare |
||||
elif specsByCol[sigCol] == '1': |
||||
for col,val in specsByCol.items(): |
||||
if col not in self.typesByCol: |
||||
if noisy: |
||||
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!! |
||||
elif self.typesByCol[col] == TYPE_INPUT: |
||||
if val == '0': |
||||
terms.append(opNot + self.signalsByCol[col]) |
||||
if nonzero and len(terms) == 1: |
||||
line = line + ') ' + opOr + '\n ('; |
||||
elif len(terms) == 1: |
||||
line = line + '\n (' |
||||
nonzero = True |
||||
elif val == '1': |
||||
terms.append(self.signalsByCol[col]) |
||||
if nonzero and len(terms) == 1: |
||||
line = line + ') ' + opOr + '\n ('; |
||||
elif len(terms) == 1: |
||||
line = line + '\n (' |
||||
nonzero = True |
||||
else: |
||||
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')') |
||||
if len(terms) > 0: |
||||
line = line + (' ' + opAnd + ' ').join(terms) |
||||
if not nonzero: |
||||
line = line + zero + ";"; |
||||
else: |
||||
line = line + ');' |
||||
self.equations.append(line) |
||||
|
||||
return self.equations |
||||
|
||||
def printv(self): |
||||
self.makeRTL() |
||||
print('\n'.join(self.equations)) |
||||
|
||||
def printinfo(self): |
||||
print('Table: ' + self.name) |
||||
print |
||||
for l in self.source: |
||||
print(l) |
||||
print |
||||
print('Signals by column:') |
||||
for col in sorted(self.signalsByCol): |
||||
print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out')) |
||||
|
||||
|
||||
#-------------------------------------------------------------------------------------------------- |
||||
# Functions |
||||
|
||||
def error(msg, quitOverride=None): |
||||
print('*** ' + msg) |
||||
if quitOverride == False: |
||||
1 |
||||
elif (quitOverride == None) or failOnError: |
||||
quit(-10) |
||||
elif quitOverride: |
||||
quit(-10) |
||||
|
||||
#-------------------------------------------------------------------------------------------------- |
||||
# Do something |
||||
|
||||
if not verilog: |
||||
openBracket = '(' |
||||
closeBracket = ')' |
||||
opAnd = 'and' |
||||
opOr = 'or' |
||||
opNot = 'not ' |
||||
zero = "'0'" |
||||
tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)') |
||||
tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)') |
||||
commentPattern = re.compile(r'^\s*?(--.*$|\s*$)') |
||||
tableLinePattern = re.compile(r'^.*?--(.*)') |
||||
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)') |
||||
else: |
||||
openBracket = '[' |
||||
closeBracket = ']' |
||||
opAnd = '&' |
||||
opOr = '+' |
||||
opNot = '~' |
||||
zero = "'b0" |
||||
tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)') |
||||
tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)') |
||||
commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)') |
||||
tableLinePattern = re.compile(r'^.*?\/\/(.*)') |
||||
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)') |
||||
|
||||
# find the lines with table spec |
||||
try: |
||||
inf = open(inFile) |
||||
for i, line in enumerate(inf): |
||||
lines.append(line.strip('\n')) |
||||
for match in re.finditer(tablePattern, line): |
||||
tableMatches.append(i) |
||||
inf.close() |
||||
except Exception as e: |
||||
error('Error opening input file ' + inFile + '\n' + str(e), True) |
||||
|
||||
# validate matches; should be paired, nothing but comments and empties; table may be named |
||||
# between them |
||||
|
||||
for i in range(0, len(tableMatches), 2): |
||||
|
||||
if i + 1 > len(tableMatches) - 1: |
||||
error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True) |
||||
|
||||
tLines = lines[tableMatches[i]:tableMatches[i+1]+1] |
||||
tableLines.append(tLines) |
||||
tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0] |
||||
if tName is None: |
||||
tName = 'noname_' + str(tableMatches[i] + 1) |
||||
tableNames.append(tName) |
||||
|
||||
for line in tLines: |
||||
if not re.match(commentPattern, line): |
||||
error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True) |
||||
|
||||
print('Found tables: ' + ', '.join(tableNames)) |
||||
|
||||
# build table objects |
||||
|
||||
for table, tName in zip(tableLines, tableNames): |
||||
print('Parsing ' + tName + '...') |
||||
namesByCol = {} |
||||
colsByName = {} |
||||
bitsByCol = {} |
||||
typesByCol = {} |
||||
specs = [] |
||||
|
||||
# parse the table - do by Table.parse() |
||||
tLines = table[1:-1] # exclude --tbl |
||||
for line in tLines: |
||||
if line.strip() == '': |
||||
continue |
||||
try: |
||||
spec = re.search(tableLinePattern, line).groups()[0] |
||||
except Exception as e: |
||||
error('Problem parsing table line:\n' + line, True) |
||||
if len(spec) > 0: |
||||
if spec[0] == 'n': |
||||
for match in re.finditer(namePattern, spec[1:]): |
||||
# col 0 is first col after n |
||||
namesByCol[match.start()] = match.groups()[0] |
||||
colsByName[match.groups()[0]] = match.start() |
||||
elif spec[0] == 'b': |
||||
for i, c in enumerate(spec[1:]): |
||||
if c == ' ' or c == '|': |
||||
continue |
||||
try: |
||||
bit = int(c) |
||||
except: |
||||
error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line) |
||||
bit = None |
||||
if i in bitsByCol and bitsByCol[i] is not None: |
||||
bitsByCol[i] = bitsByCol[i]*10+bit |
||||
else: |
||||
bitsByCol[i] = bit |
||||
elif spec[0] == 't': |
||||
for i, c in enumerate(spec[1:]): |
||||
if c.lower() == 'i': |
||||
typesByCol[i] = TYPE_INPUT |
||||
elif c.lower() == 'o': |
||||
typesByCol[i] = TYPE_OUTPUT |
||||
elif c.lower() == '*': |
||||
typesByCol[i] = TYPE_SKIP |
||||
elif c != ' ': |
||||
error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line) |
||||
typesByCol[i] = None |
||||
else: |
||||
typesByCol[i] = None |
||||
elif spec[0] == 's': |
||||
specsByCol = {} |
||||
for i, c in enumerate(spec[1:]): |
||||
if c == '0' or c == '1': |
||||
specsByCol[i] = c |
||||
specs.append(specsByCol) |
||||
else: |
||||
#print('other:') |
||||
#print(line) |
||||
1 |
||||
|
||||
# create table object |
||||
|
||||
# add strand to name where defined; don't combine for now into vector |
||||
# consecutive strands belong to the last defined name |
||||
lastName = None |
||||
lastCol = 0 |
||||
signalsByCol = {} |
||||
|
||||
for col,name in namesByCol.items(): # load with unstranded names |
||||
signalsByCol[col] = name |
||||
|
||||
# sort by col so consecutive columns can be easily tracked |
||||
#for col,val in bitsByCol.items(): # update with stranded names |
||||
for col in sorted(bitsByCol): |
||||
val = bitsByCol[col] |
||||
|
||||
if col > lastCol + 1: |
||||
lastName = None |
||||
if val is None: |
||||
lastName = None |
||||
if col in namesByCol: |
||||
if val is None: |
||||
signalsByCol[col] = namesByCol[col] |
||||
else: |
||||
lastName = namesByCol[col] |
||||
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket |
||||
elif lastName is not None: |
||||
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket |
||||
else: |
||||
error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.') |
||||
lastCol = col |
||||
|
||||
t = Table(tName) |
||||
t.source = table |
||||
t.signalsByCol = signalsByCol |
||||
t.typesByCol = typesByCol |
||||
t.specs = specs |
||||
|
||||
tables[tName] = t |
||||
|
||||
for name in tables: |
||||
t = tables[name] |
||||
t.validate() |
||||
t.makeRTL() |
||||
|
||||
print() |
||||
print('Results:') |
||||
|
||||
# find the lines with generate spec and replace them with new version |
||||
outLines = [] |
||||
inTable = False |
||||
for i, line in enumerate(lines): |
||||
if not inTable: |
||||
match = re.search(tableGenPattern, line) |
||||
if match is not None: |
||||
tName = match.groups(1)[0] |
||||
if tName not in tables: |
||||
if tName == 1: |
||||
tName = '<blank>' |
||||
error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True) |
||||
else: |
||||
outLines.append(line) |
||||
outLines += tables[tName].equations |
||||
tables[tName].added = True |
||||
inTable = True |
||||
else: |
||||
outLines.append(line) |
||||
else: |
||||
match = re.search(tableGenPattern, line) |
||||
if match is not None: |
||||
if match.groups(1)[0] != tName: |
||||
error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True) |
||||
outLines.append(line) |
||||
inTable = False |
||||
else: |
||||
1#print('stripped: ' + line) |
||||
|
||||
if backup: |
||||
try: |
||||
copyfile(inFile, backupFile) |
||||
except Exception as e: |
||||
error('Error creating backup file!\n' + str(e), True) |
||||
|
||||
try: |
||||
of = open(outFile, 'w') |
||||
for line in outLines: |
||||
of.write("%s\n" % line) |
||||
except Exception as e: |
||||
error('Error writing output file ' + outFile + '!\n' + str(e), True) |
||||
|
||||
print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames)) |
||||
notAdded = {} |
||||
for table in tables: |
||||
if not tables[table].added: |
||||
notAdded[table] = True |
||||
print('Output file: ' + outFile) |
||||
if backup: |
||||
print('Backup file: ' + backupFile) |
||||
if len(notAdded) != 0: |
||||
error('Tables generated but not added to file! ' + ', '.join(notAdded)) |
||||
Loading…
Reference in new issue