add pd
openpowerwtf
1 year ago
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9a741fa9b0
commit
2f35e537e5
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# Synthesis
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```
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yosys -s synth.yo &> yosys.txt
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```
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## Arrays
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```
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grep tri_1 verilog/work/*
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(
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verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(
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verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(
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verilog/work/rv.v: tri_144x78_2r4w
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(
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grep tri_2 verilog/work/*
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verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(
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grep tri_3 verilog/work/*
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verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(
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grep tri_5 verilog/work/*
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verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(
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grep tri_6 verilog/work/*
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verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(
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verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(
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verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
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grep tri_bht verilog/work/*
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
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verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(
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grep tri_cam verilog/work/*
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verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(
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verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(
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grep tri_iuq verilog/work/*
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verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
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```
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## By Unit
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* XU (GPR, SPR)
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(
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verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
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* FU (FPR)
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(
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* RV (LQ)
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verilog/work/rv.v: tri_144x78_2r4w
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* IU (CPL, ERAT, DIR, DATA, BTB, BHT)
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verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
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verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(
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verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir(
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verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(
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verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
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verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(
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* LQ (ERAT, DIR, DATA. PFETCH, RLDQ, STQ)
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verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(
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verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(
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verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(
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verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(
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verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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* MMU (TLB)
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(
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verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(
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## By Type
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### Normal
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* tri_144x78_2r4w
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
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verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
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verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(
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verilog/work/rv.v: tri_144x78_2r4w
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* tri_64x72_1r1w
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verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
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verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(
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* tri_512x162_4w_0
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verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(
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* tri_32x70_2w_1r1w
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verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(
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* tri_256x144_8w_1r1w
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verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(
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* tri_64x34_8w_1r1w
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verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
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* tri_64x144_1r1w
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verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(
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* tri_128x168_1w_0
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
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verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(
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* tri_128x16_1r1w_1
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verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(
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### Complex
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#### Branch History
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* tri_bht_1024x8_1r1w
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
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verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
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* inner array:
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tri_512x16_1r1w_1 bht0(
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* tri_bht_512x4_1r1w
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verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(
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* inner array:
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tri_512x16_1r1w_1 bht0(
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#### Completion
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* tri_iuq_cpl_arr
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verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
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* inner arrays (143)
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
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* =2x64x143
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#### ERATs (CAM)
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* tri_cam_16x143_1r1w1c
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verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(
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* tri_cam_32x143_1r1w1c
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verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(
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## Summary
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* the difficult arrays are the 2r4w (gpr, fpr, rv) and the cams; everything else is 1r1w
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* cpl array is 1r1w (written in iu6, read in cp0), arranged even/odd for i0/i1; CPL_Q_DEPTH=32 means 32 even + 32 odd(?)
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* some of these are directly changed with gen parameters; others may be do-able with some combo or parameters/spr settings/simple logic changes
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* GPR rename pool size
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* FPR rename pool size
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* completion queue depth
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* IERAT size
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* IC size
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* IC ways
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* BTB size
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* BHT size
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* DERAT size
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* DC size
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* DC ways
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* TLB size
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* TLB ways
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* e.g. no xlate, small caches
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* IERAT, DERAT replaced with single-entry always-hit (no CAMs)
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* IC, DC 1W small data
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* no TLB
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* alter BTB, BHT, rename, completion as necessary
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* mmu logic (and fpu if not needed) could be dropped
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@ -1,13 +0,0 @@
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#read_verilog ../verilog/unisims
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# blockbox versions
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read_verilog ../verilog/unisims_synth
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read_verilog -I../verilog/trilib ../verilog/trilib/*
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read_verilog -I../verilog/trilib ../verilog/work/*
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hierarchy -top c
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proc; opt; memory -nomap; opt -fast
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#check -assert
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#synth -top c
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@ -1 +0,0 @@
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../verilog
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