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      dev/sim/verilator/readme.md

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dev/sim/verilator/readme.md

@ -1,5 +1,17 @@ @@ -1,5 +1,17 @@
# Verilator

##
* verilator now successfully runs, once the nclk[] changes were completed to separate clk and rst, and
remove lcb's driving lclk's

```
verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator.txt
```

* about 5 non-scan UNOPTFLATs

## Experiments

### core-only initial experiment

```
@ -37,15 +49,6 @@ obj_dir/Va2owb @@ -37,15 +49,6 @@ obj_dir/Va2owb

# Verilator Debug

* verilator now successfully runs, once the nclk[] changes were completed to separate clk and rst, and
remove lcb's driving lclk's

```
verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator.txt
```

* about 5 non-scan UNOPTFLATs

##### Old Stuff

* install multiple versions concurrently

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