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litex 64le

master
openpowerwtf 3 months ago
parent
commit
5063e6b2d4
  1. 11
      dev/build/litex/a2o/core.py
  2. 156
      dev/build/litex/a2o/crt0.S

11
dev/build/litex/a2o/core.py

@ -20,13 +20,17 @@ CPU_VARIANTS = { @@ -20,13 +20,17 @@ CPU_VARIANTS = {

#wtf doesnt do anything, but you can somehow do it by using -Xassembler in gcc flags
GAS_FLAGS = {

'WB_32BE' : '-defsym BIOS_32=1',
'WB_64LE' : '-defsym BIOS_LE=1'
}

#wtf skip crc and ram memtest for now!
# i hacked /data/projects/pythondata-software-picolibc/pythondata_software_picolibc/data/meson.build to force io_long_long=false for ppc32!!!
# and to add 'ppc' family. need to use original for 64b!!!!!!!!!!!!!!!!!!
# edit then pip3 install .

GCC_FLAGS = {
'WB_32BE' : '-mcpu=a2 -m32 -mbig-endian -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1 -DCONFIG_BIOS_NO_BOOT=1 -DCONFIG_BIOS_NO_CRC=1 -DCONFIG_MAIN_RAM_INIT=1',
'WB_32BE' : '-mcpu=a2 -m32 -mbig-endian -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1',
'WB_64LE' : '-mcpu=a2 -m64 -mlittle-endian -mabi=elfv2 -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_LE=1'
}

@ -43,7 +47,7 @@ class A2O(CPU, AutoCSR): @@ -43,7 +47,7 @@ class A2O(CPU, AutoCSR):
linker_output_format = 'elf64-powerpcle'

nop = 'nop'
io_regions = {0xF0000000: 0x10000000} # origin, length
io_regions = {0xFFF00000: 0x100000} # origin, length

@property
def mem_map(self):
@ -60,6 +64,7 @@ class A2O(CPU, AutoCSR): @@ -60,6 +64,7 @@ class A2O(CPU, AutoCSR):
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += ' -D__a2o__'
flags += ' -DCONFIG_BIOS_NO_BOOT=1 -DCONFIG_BIOS_NO_CRC=1 -DCONFIG_MAIN_RAM_INIT=1' #wtf skip crc and ram memtest for now!
return flags

def __init__(self, platform, variant='WB'):

156
dev/build/litex/a2o/crt0.S

@ -37,14 +37,12 @@ @@ -37,14 +37,12 @@
.set BIOS_STACK_1,_fstack-8

.macro load32 rx,v
li \rx,0
oris \rx,\rx,\v>>16
lis \rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
.endm

.macro load16swiz rx,v
li \rx,0
ori \rx,\rx,(\v<<8)&0xFF00
lis \rx,(\v<<8)&0xFF00
ori \rx,\rx,(\v>>8)&0x00FF
.endm

@ -75,9 +73,9 @@ @@ -75,9 +73,9 @@
.set BIOS_STACK_0,_stack_0
.endif

#.ifndef BIOS_STACK_1
#.set BIOS_STACK_1,_stack_1
#.endif
.ifndef BIOS_STACK_1
.set BIOS_STACK_1,_stack_1
.endif

.section .text

@ -85,11 +83,71 @@ @@ -85,11 +83,71 @@

.org 0x000
_start:
int_000:
b boot_start

# ints need to handle save/restore and call to isr (like uart_isr())
# enable in a2node when it's safe (stack set up, etc.)
.ifdef BIOS_LE
# a2o boots in 32Be w/erats set up for BE; rewrite I[15],D[31]
# 0000000000000240 <_start>:
# 240: 00 8c 60 3c lis r3,-29696
# 244: 1f 00 00 38 li r0,31
# 248: 95 00 40 38 li r2,149
# 24c: 00 00 80 38 li r4,0
# 250: 3f 02 00 39 li r8,575
# 254: a6 fb 7c 7c mtspr 1020,r3
# 258: a6 11 40 7c eratwe r2,r0,2
# 25c: a6 09 80 7c eratwe r4,r0,1
# 260: a6 01 00 7d mtfprwa f8,r0
# 264: 2c 01 00 4c isync
# 268: 00 88 60 3c lis r3,-30720
# 26c: 0f 00 00 38 li r0,15
# 270: bf 00 40 38 li r2,191
# 274: 00 00 80 38 li r4,0
# 278: 3f 02 00 39 li r8,575
# 27c: a6 fb 7c 7c mtspr 1020,r3
# 280: a6 11 40 7c eratwe r2,r0,2
# 284: a6 09 80 7c eratwe r4,r0,1
# 288: a6 01 00 7d mtfprwa f8,r0
# 28c: 2c 01 00 4c isync
# 290: 00 00 40 39 li r10,0
# 294: 02 80 4a 65 oris r10,r10,32770
# 298: 00 b0 4a 61 ori r10,r10,45056
# 29c: 24 01 40 7d mtmsr r10
# 2a0: 2c 01 00 4c isync

.long 0x008c603c
.long 0x1f000038
.long 0x95004038
.long 0x00008038
.long 0x3f020039
.long 0xa6fb7c7c
.long 0xa611407c
.long 0xa609807c
.long 0xa601007d
.long 0x2c01004c
.long 0x0088603c
.long 0x0f000038
.long 0xbf004038
.long 0x00008038
.long 0x3f020039
.long 0xa6fb7c7c
.long 0xa611407c
.long 0xa609807c
.long 0xa601007d
.long 0x2c01004c
# stay in 32b mode until done with common code
#.long 0x00004039
#.long 0x02804a65
#.long 0x00b04a61
#.long 0x2401407d
#.long 0x2c01004c
#.long 0x02040048
# isync
# li r10,0
# oris r10,r10,32770
# ori r10,r10,45056
# mtmsr r10
# isync

.else

# critical input
.org 0x020
@ -110,6 +168,13 @@ int_040: @@ -110,6 +168,13 @@ int_040:
int_060:
b .

.endif

b boot_start

# ints need to handle save/restore and call to isr (like uart_isr())
# enable in a2node when it's safe (stack set up, etc.)

# isi
.org 0x080
int_080:
@ -252,18 +317,20 @@ boot_start: @@ -252,18 +317,20 @@ boot_start:
bne init_t123

lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
mtspr mmucr0,r3

.ifndef BIOS_LE
# derat 31 @00000000
li r0,0x001F # entry #31
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync
.endif

load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63

@ -280,7 +347,8 @@ boot_start: @@ -280,7 +347,8 @@ boot_start:

# derat 29 @<CSR_START> I=1!!!
li r0,0x001D # entry #29
ori r10,r10,0x0F00 # word 2 with WIMG=F
#ori r10,r10,0x0F00 # word 2 with WIMG=F - doesn't work for 64LE
li r10,0x0F3F # WIMG=F BE
load32 r4,CSR_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
load32 r8,CSR_START
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
@ -291,18 +359,20 @@ boot_start: @@ -291,18 +359,20 @@ boot_start:
isync

lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
mtspr mmucr0,r3

.ifndef BIOS_LE
# ierat 15 @00000000
li r0,0x000F # entry #15
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync
.endif

# *** leave the init'd entry 14 for MT access to FFFFFFC0
# ierat 13 @<BIOS_START>
@ -330,6 +400,8 @@ init_t0: @@ -330,6 +400,8 @@ init_t0:
########################################################################################################################################
# VMA/LMA: copy .data, clear .bss
rominit:
.ifdef BIOS_32

lis r1,_fdata_rom@h
ori r1,r1,_fdata_rom@l
lis r2,_fdata@h
@ -341,6 +413,23 @@ rominit: @@ -341,6 +413,23 @@ rominit:
lis r5,_ebss@h
ori r5,r5,_ebss@l

.else

bl +4
1: mflr r12
addis r12,r12,(.TOC.-1b)@h
addi r12,r12,(.TOC.-1b)@l # now gots toc
ld r1,_fdata_rom@got(r12)
ld r2,_fdata@got(r12)
ld r3,_edata_rom@got(r12)
ld r4,_fbss@got(r12)
ld r5,_ebss@got(r12)
ld r6,_fstack@got(r12)
addi r6,r6,-32

.endif


subf r9,r1,r3
srwi. r9,r9,2
beq romcopy_done
@ -389,13 +478,19 @@ romclear_done: @@ -389,13 +478,19 @@ romclear_done:
# lis r1,_stack_0@h
# ori r1,r1,_stack_0@l
# this requires data load

.ifdef BIOS_32
lwz r1,stack_0(r0)
.else
mr r1,r6
.endif

b boot_complete

# except T0

init_t123:
# NEEDS 64LE VERSION!!! once i figure out the right way

# set up BIOS msr

@ -411,14 +506,45 @@ init_t123: @@ -411,14 +506,45 @@ init_t123:
boot_complete:

# set up thread and hop to it
.ifdef BIOS_32

lis r3,main@h
ori r3,r3,main@l
mtctr r3
mfspr r3,tir # who am i?
mfspr r3,tir # who am i?

.else
bl +4
0: mflr r2
addis r2,r2,(.TOC.-0b)@h
addi r2,r2,(.TOC.-0b)@l # set toc
ld r3,main@got(r2)
addi r3,r3,8 # <main+8>
mtctr r3
li r3,0 # argc

.endif

bctrl
b kernel_return

wtf: # huh? what did linux guys do to the good ol 32b stuff?
bl main
ba main
ba main@got
lwz r1,main(r0)
lwz r1,main@got(r0)
uwatt:
bl +4
0: mflr r2
# /* Get our TOC */
addis r1,r2,(.TOC.-0b)@h
addi r2,r2,(.TOC.-0b)@l
ld r3,_fdata@got(r2)
wtf2:
ld r3,main@got(r2)


# ------------------------------------------------------------------------------------------------------------------------------

.ifdef BIOS_32

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