change verilator publics

dev/verilog/work/c.v

@@ -752,7 +752,7 @@ module c(
    wire [0:`THREADS-1] 		cp_flush;
    wire [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag;
    wire [0:`ITAG_SIZE_ENC-1] cp_t0_flush_itag;
-   wire [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar;
+   wire [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar /* verilator public */;
    wire [0:`THREADS-1]		cp_axu_i0_t1_v;
    wire [0:`THREADS-1]		cp_axu_i1_t1_v;
 
@@ -763,7 +763,7 @@ module c(
 
    wire [0:`ITAG_SIZE_ENC-1] 					cp_t1_next_itag;
    wire [0:`ITAG_SIZE_ENC-1] 					cp_t1_flush_itag;
-   wire [62-`EFF_IFAR_ARCH:61] 					cp_t1_flush_ifar;
+   wire [62-`EFF_IFAR_ARCH:61] 					cp_t1_flush_ifar /* verilator public */;
    wire [0:2] 							cp_axu_t1_i0_t1_t;
    wire [0:`GPR_WIDTH_ENC-1] 					cp_axu_t1_i0_t1_p;
    wire [0:2] 							cp_axu_t1_i1_t1_t;

dev/verilog/work/iuq_cpl.v

@@ -558,8 +558,8 @@ module iuq_cpl(
    wire [0:entry_length-1]       di1;
    wire [0:entry_length-1]       do0;
    wire [0:entry_length-1]       do1;
-   wire [62-`EFF_IFAR_WIDTH:61]   cp2_i0_ifar;
-   wire [62-`EFF_IFAR_WIDTH:61]   cp2_i1_ifar;
+   wire [62-`EFF_IFAR_WIDTH:61]   cp2_i0_ifar /*verilator public*/;
+   wire [62-`EFF_IFAR_WIDTH:61]   cp2_i1_ifar /*verilator public*/;
    wire                          cp2_i0_bp_pred;
    wire                          cp2_i1_bp_pred;
    wire                          cp2_i0_br_pred;
@@ -666,8 +666,8 @@ module iuq_cpl(
    wire                          cp2_i1_btb_entry;
    wire [0:1]                    cp2_i0_btb_hist;
    wire [0:1]                    cp2_i1_btb_hist;
-   wire                          cp2_i0_completed;
-   wire                          cp2_i1_completed;
+   wire                          cp2_i0_completed /*verilator public*/;
+   wire                          cp2_i1_completed /*verilator public*/;
    wire [1:`ITAG_SIZE_ENC-1]      cp0_i0_completed_itag;
    wire [1:`ITAG_SIZE_ENC-1]      cp0_i1_completed_itag;
    wire                          cp2_i0_axu_exception_val;