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@ -31,7 +31,8 @@
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// interface to wb32
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//
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// could pass core reset through here to allow this to be configured first
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// could add config space
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// could add config space, or just use csr interface
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//
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`include "tri_a2o.vh"
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`ifndef A2NODE_CFG
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@ -60,6 +61,7 @@ module a2l2wb #(
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// 110 write mask rst
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// 111 write mask xor
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// also, should it be edge-triggered (single pulse from nop->cmd)?
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// should cfg_q just be implemented in the csr itself??
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input cfg_wr,
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output [0:31] status,
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@ -234,8 +236,13 @@ module a2l2wb #(
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wire [0:4] req_tag;
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wire [0:2] req_len;
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wire [0:255] req_st_dat;
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wire [0:255] st_dat_swizzle;
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wire [0:31] req_st_be;
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wire [0:7] req_st_we;
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wire req_endian;
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wire req_st_4;
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wire req_st_8;
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wire req_st_16;
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wire rld_coming;
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wire rld_valid;
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@ -254,6 +261,7 @@ module a2l2wb #(
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wire qw_sel_3;
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wire [0:7] tb_pulse_val;
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wire tb_pulse_toggle;
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wire [0:3] intr_enable;
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// FF
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always @(posedge clk) begin
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@ -390,6 +398,7 @@ endgenerate
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assign req_tag = req_q[10:14];
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assign req_adr = req_q[15:15+`REAL_IFAR_WIDTH-1];
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assign req_len = req_q[57:59];
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assign req_endian = req_q[64];
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assign req_st_be = std_q[0:31];
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assign req_st_we[0] = |std_q[0:3];
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@ -558,10 +567,35 @@ generate if (MEM_MODE == 2) begin
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dat_sel == 2'b10 ? req_st_be[8:11] :
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req_st_be[12:15];
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assign wb_datw = dat_sel == 2'b00 ? req_st_dat[0:31] :
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dat_sel == 2'b01 ? req_st_dat[32:63] :
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dat_sel == 2'b10 ? req_st_dat[64:95] :
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req_st_dat[96:127];
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/*
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assign req_st_4 = req_st_we == 4'b1000;
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assign req_st_8 = req_st_we == 4'b1100;
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assign req_st_16 = req_st_we == 4'b1111;
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assign st_dat_swizzle[0:31] = ~req_endian ? req_st_dat[0:31] :
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req_st_4 ? {req_st_dat[24:31], req_st_dat[16:23], req_st_dat[8:15], req_st_dat[0:7]} :
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req_st_8 ? {req_st_dat[56:63], req_st_dat[48:55], req_st_dat[40:47], req_st_dat[32:39]} :
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{req_st_dat[120:127], req_st_dat[112:119], req_st_dat[104:111], req_st_dat[96:103]};
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assign st_dat_swizzle[32:63] = ~req_endian ? req_st_dat[32:63] :
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req_st_8 ? {req_st_dat[24:31], req_st_dat[16:23], req_st_dat[8:15], req_st_dat[0:7]} :
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{req_st_dat[88:95], req_st_dat[80:87], req_st_dat[72:79], req_st_dat[64:71]};
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assign st_dat_swizzle[64:95] = ~req_endian ? req_st_dat[64:95] :
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{req_st_dat[56:63], req_st_dat[48:55], req_st_dat[40:47], req_st_dat[32:39]};
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assign st_dat_swizzle[96:127] = ~req_endian ? req_st_dat[96:127] :
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{req_st_dat[24:31], req_st_dat[16:23], req_st_dat[8:15], req_st_dat[0:7]};
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*/
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assign st_dat_swizzle = req_st_dat;
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assign wb_datw = dat_sel == 2'b00 ? st_dat_swizzle[0:31] :
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dat_sel == 2'b01 ? st_dat_swizzle[32:63] :
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dat_sel == 2'b10 ? st_dat_swizzle[64:95] :
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st_dat_swizzle[96:127];
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end
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endgenerate
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@ -609,9 +643,9 @@ endgenerate
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// these have to be examined/cleared at the source
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assign intr_d = {4'b0, softwareInterrupt, timerInterrupt, externalInterruptS, externalInterrupt};
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// map for now
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assign an_ac_crit_interrupt[0] = intr_q[4];
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assign an_ac_perf_interrupt[0] = intr_q[5];
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assign an_ac_ext_interrupt[0] = intr_q[6] | intr_q[7];
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assign an_ac_crit_interrupt[0] = intr_q[4] & intr_enable[0];
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assign an_ac_perf_interrupt[0] = intr_q[5] & intr_enable[1];
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assign an_ac_ext_interrupt[0] = (intr_q[6] & intr_enable[2]) | (intr_q[7] & intr_enable[3]);
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assign err_d = {(new_req & ~cmdseq_idle), 7'b0};
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assign an_ac_checkstop = err_q != 0;
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@ -636,15 +670,16 @@ endgenerate
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assign an_ac_sleep_en = cfg_q[26];
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assign an_ac_hang_pulse = cfg_q[25];
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// threaded
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// TO
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assign an_ac_pm_thread_stop[0] = cfg_q[0];
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assign an_ac_pm_fetch_halt[0] = cfg_q[1];
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assign intr_enable = cfg_q[4:7]; // crit,perf,ext,extS
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assign status = {ac_an_pm_thread_running[0], ac_an_special_attn[0], ac_an_machine_check[0],
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ac_an_debug_trigger[0], ac_an_power_managed, ac_an_rvwinkle_mode, 2'b0,
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8'b0, 8'b0,
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4'b0, ac_an_checkstop[0:2], err_q
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intr_q, ac_an_checkstop[0:2], err_q
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};
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