syntax error

8 months ago · d8d9fb6a99
parent d80e4f489f
commit d8d9fb6a99
1 changed files with 1 additions and 1 deletions
--- a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v
+++ b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v
@ -139,6 +139,6 @@ module tri_aoi22_nlats_wlcb (

      assign scout = ZEROS;

-      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b (|scin);
+      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin;
   endgenerate
 endmodule