nclk changes

pull/18/head
openpowerwtf 2 years ago
parent 2a2caf6797
commit e548eafd69

@ -269,7 +269,7 @@ async def A2L2Driver(dut, sim):

while ok and not sim.done:

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

sim.a2o.root.an_ac_req_ld_pop.value = 0
sim.a2o.root.an_ac_req_st_pop.value = 0
@ -283,12 +283,12 @@ async def A2L2Driver(dut, sim):
sim.a2o.root.an_ac_reld_l1_dump.value = 0
sim.a2o.root.an_ac_req_spare_ctrl_a1.value = 0

if sim.threads == 1:
if sim.a2o.config.threads == 1:
sim.a2o.root.an_ac_reservation_vld.value = 0
sim.a2o.root.an_ac_stcx_complete.value = 0
sim.a2o.root.an_ac_stcx_pass.value = 0
else:
for i in range(sim.threads):
for i in range(sim.a2o.config.threads):
sim.a2o.root.an_ac_reservation_vld[i].value = 0
sim.a2o.root.an_ac_stcx_complete[i].value = 0
sim.a2o.root.an_ac_stcx_pass[i].value = 0
@ -316,7 +316,8 @@ async def A2L2Driver(dut, sim):

tt = hex(sim.a2o.root.ac_an_req_ttype, 2)
transType = transTypes[tt]
tid = hex(sim.a2o.root.ac_an_req_thread)
tid = sim.a2o.root.ac_an_req_thread.value >> 1
ditc = sim.a2o.root.ac_an_req_thread.value & 0x1
ra = hex(sim.a2o.root.ac_an_req_ra, 8)
tag = hex(sim.a2o.root.ac_an_req_ld_core_tag, 2)
lenEnc = hex(sim.a2o.root.ac_an_req_ld_xfr_len)
@ -414,7 +415,7 @@ async def A2L2Checker(dut, sim):
sim.msg(f'{me}: started.')

while ok:
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)


# A2L2 Monitor
@ -435,7 +436,7 @@ async def A2L2Monitor(dut, sim, watchTrans=False):

while start and ok:

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if sim.a2o.root.ac_an_req.value: # should first check ac_an_req_pwr_token prev cyc


@ -35,13 +35,13 @@ async def A2OConfig(dut, sim):
cpcr4_q = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_l2
cpcr4_act = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_wren

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if sim.a2o.config.creditsLd is not None:
creditsLd.value = Force(sim.a2o.config.creditsLd)
creditsLdMax.value = Force(sim.a2o.config.creditsLd)
sim.msg(f'A2O: load credits changed from {creditsLd.value.integer} to {sim.a2o.config.creditsLd}.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
creditsLd.value = Release()
else:
sim.msg(f'A2O: load credits = {creditsLd.value.integer}.')
@ -50,7 +50,7 @@ async def A2OConfig(dut, sim):
creditsSt.value = Force(sim.a2o.config.creditsSt)
creditsStMax.value = Force(sim.a2o.config.creditsSt)
sim.msg(f'A2O: store credits changed from {creditsSt.value.integer} to {sim.a2o.config.creditsSt}.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
creditsSt.value = Release()
else:
sim.msg(f'A2O: store credits = {creditsSt.value.integer}.')
@ -59,7 +59,7 @@ async def A2OConfig(dut, sim):
v = 1 if sim.a2o.config.creditsLdStSingle else 0
creditsLdStSingle.value = Force(v)
sim.msg(f'A2O: only one load OR store allowed when credits=1/1.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
#creditsLdStSingle.value = Release() # to release have to set _q with xucr0_d[51] and xucr0_act
elif sim.a2o.root.lq0.lsq.arb.load_cred_cnt_q.value.integer == 1 and sim.a2o.root.lq0.lsq.arb.store_cred_cnt_q.value.integer == 1 and sim.a2o.root.lq0.lsq.arb.spr_xucr0_cred_q.value.integer == 1:
sim.msg(f'A2O: single-credit mode is enabled.')
@ -72,7 +72,7 @@ async def A2OConfig(dut, sim):
v = v << 2
v = (lsucr0_q.value.integer & ~0x4) | v
lsucr0_d.value = Force(v)
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
lsucr0_d.value = Release()
sim.msg(f'A2O: LSUCR0 = {hex(lsucr0_q.value), 8}')

@ -82,16 +82,16 @@ async def A2OConfig(dut, sim):
sim.msg(f'A2O: Setting CPCR4[SQ_CNT] = {v}.')
v = v << 0
v = (cpcr4_q[0].value.integer & ~0x1F) | v
await RisingEdge(dut.clk_1x) # need cuz of act?
await RisingEdge(sim.sigClk) # need cuz of act?
cpcr4_d[0].value = Force(v)
cpcr4_act.value = Force(1)
await RisingEdge(dut.clk_1x)
await RisingEdge(dut.clk_1x) # need cuz of act?
await RisingEdge(sim.sigClk)
await RisingEdge(sim.sigClk) # need cuz of act?
cpcr4_d[0].value = Release()
cpcr4_act.value = Release()
sim.msg(f'A2O: CPCR4 = {hex(cpcr4_q[0], 8)}')

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

async def A2ODriver(dut, sim):
"""A2O Core Driver"""
@ -109,7 +109,7 @@ async def A2ODriver(dut, sim):
sim.msg('A2O Driver: nothing to do.')

#while ok and not sim.done:
# await RisingEdge(dut.clk_1x)
# await RisingEdge(sim.sigClk)


# A2O Checker
@ -131,7 +131,7 @@ async def A2OChecker(dut, sim):

while ok:

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if not sim.resetDone:
continue
@ -149,6 +149,8 @@ async def A2OMonitor(dut, sim):
ok = True
sim.msg(f'{me}: started.')

#wtf NEEDS THREADING! separate hang/loop/pass/fail checks for each

# completions
iu0Comp = sim.a2o.root.iu_lq_i0_completed
iu0CompIFAR = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar
@ -157,7 +159,7 @@ async def A2OMonitor(dut, sim):
iuCompFlushIFAR = sim.a2o.root.cp_t0_flush_ifar
cp3NIA = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions

# GPR ppol and arch map
# GPR pool and arch map
gprCompMap = []
lastGprCompMap = []
#wtf check what 33:36 are!
@ -221,11 +223,13 @@ async def A2OMonitor(dut, sim):

while ok:

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if not sim.resetDone:
continue

#wtf NEED SMT

# allow registered callbacks to be called here
stack = sim.mem.dump(0x1FD00, 0x1FFFF, cols=8, trimLeadingZeros=True, trimTrailingZeros=True)
if stack != lastStack:
@ -339,6 +343,7 @@ class A2OCore(DotMap):
self.iarPass = None
self.iarFail = None
self.config = DotMap({
'threads' : 1,
'creditsLd': None,
'creditsSt': None,
'creditsLdStSingle': None,

@ -8,7 +8,7 @@ VERILOG_ROOT = ../../verilog

# litex version
NODE = $(VERILOG_ROOT)/a2o_litex
COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(NODE) -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(NODE) -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options


@ -6,10 +6,11 @@ SIM ?= icarus
# icarus
VERILOG_ROOT = ../../verilog

#NODE = a2node
# a2node_verilator has some test, etc. inputs tied in rtl
# also has l/s credits set to 1 in defines
COMPILE_ARGS = -I$(VERILOG_ROOT)/a2node_verilator -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/a2node_verilator

NODE = $(VERILOG_ROOT)/a2node_verilator
COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work -y$(NODE)
# other options

# rtl

@ -3,7 +3,7 @@
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

SIM_BUILD ?= build_smt2
SIM_BUILD ?= build_smt
SIM ?= icarus

# options
@ -19,7 +19,7 @@ SIM ?= icarus

VERILOG_ROOT = ../../verilog

COMPILE_ARGS = -I$(VERILOG_ROOT)/smt2 -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
COMPILE_ARGS = -I$(VERILOG_ROOT)/smt -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options

@ -31,6 +31,7 @@ TOPLEVEL = cocotb_icarus

# python test
MODULE = tb
TESTCASE = tb_smt

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim
@ -40,5 +41,5 @@ build: clean sim fst
run: sim fst

fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd
vcd2fst a2ocore.vcd a2ocore_smt.fst
rm a2ocore.vcd

@ -24,7 +24,7 @@ SIM ?= icarus

VERILOG_ROOT = ../../verilog

COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options

@ -36,6 +36,7 @@ TOPLEVEL = cocotb_icarus

# python test
MODULE = tb
TESTCASE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim
@ -47,5 +48,5 @@ run: sim fst
vcd: sim

fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd
vcd2fst a2ocore.vcd a2ocore.fst
rm a2ocore.vcd

@ -6,9 +6,8 @@ SIM ?= icarus
# icarus
VERILOG_ROOT = ../../verilog

# a2node_verilator has some test, etc. inputs tied in rtl
# also has l/s credits set to 1 in defines
COMPILE_ARGS = -I$(VERILOG_ROOT)/a2node_wb -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/a2node_wb -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
NODE = $(VERILOG_ROOT)/a2node_wb
COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(NODE) -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options


@ -23,28 +23,23 @@ class Sim(DotMap):
self.resetDone = False

# defaults
self.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm

self.sigClk = None
self.sigRst = None
self.sigClk2x = None
self.sigClk4x = None

self.threads = None
self.resetAddr = None # 0xFFFFFFFC
self.resetOp = 0x48000002
self.memFiles = None

self.resetCycle = 10
self.hbCycles = 100
self.clk2x = True
self.clk4x = False
self.resetAddr = 0xFFFFFFFC
self.resetOp = 0x48000002
self.maxCycles = 500
self.memFiles = None

self.config = DotMap()
# these should be in a2 core class
self.config.core = DotMap({
'creditsLd': None,
'creditsSt': None,
'creditsLdStSingle': None,
'lsDataForward' : None,
'cpcr4_sq_cnt' : None
})
self.config.a2l2 = DotMap({
'badAddr': [('E0','E0', 'IRW')]
})

# json
if cfg is not None:
pass

@ -1 +0,0 @@
+timescale+1ns/1ps

@ -1,13 +1,12 @@

`include "tri_a2o.vh"

`timescale 1ns/1ps

// might add some sim-only lines to enable clks, etc.
`timescale 1ns / 1ns

module cocotb_icarus (

input[0:`NCLK_WIDTH-1] nclk,
input clk,
input reset,
input scan_in,
output scan_out,

@ -158,7 +157,8 @@ c c0(
// EXPAND_TYPE => EXPAND_TYPE
// );

.nclk(nclk),
.clk(clk),
.rst(rst),
.scan_in(scan_in),
.scan_out(scan_out),

@ -301,7 +301,7 @@ c c0(
);

initial begin
$dumpfile ("wtf-coco.vcd");
$dumpfile ("a2ocore.vcd");
// you can do it by levels and also by module so could prune down
$dumpvars;
// need to explicitly specify arrays for icarus
@ -310,12 +310,4 @@ initial begin
#1;
end

// see if coco lets me risingedge() these
wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule

@ -1,13 +1,12 @@

`include "tri_a2o.vh"

`timescale 1ns/1ps

// might add some sim-only lines to enable clks, etc.
`timescale 1ns / 1ns

module cocotb_icarus_node (

input[0:`NCLK_WIDTH-1] nclk,
input clk,
input rst,
input scan_in,
output scan_out,

@ -119,7 +118,8 @@ module cocotb_icarus_node (
);

a2owb c0 (
.nclk(nclk),
.clk(clk),
.rst(rst),
.scan_in(scan_in),
.scan_out(scan_out),

@ -235,12 +235,4 @@ initial begin
#1;
end

// see if coco lets me risingedge() these
wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule

@ -5,8 +5,7 @@

module cocotb (

input clk_1x,
input clk_2x,
input clk,
input rst,

input [0:31] cfg_dat,
@ -30,8 +29,7 @@ module cocotb (
);

a2owb c0 (
.clk_1x(clk_1x),
.clk_2x(clk_2x),
.clk(clk),
.rst(rst),

.cfg_wr(cfg_wr),

@ -24,9 +24,3 @@ make -f Makefile.node build |& grep -v Anac
make -f Makefile.wb build |& grep -v Anac
``

* update wrapper to include normal Litex, etc. I/O (WB plus ints, config, etc.)
* add Litex core definition (migen)

* can add L2 mem
* can add multiple core intefaces (SMP)
* can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)

@ -22,7 +22,6 @@ from A2L2 import *
async def init(dut, sim):
"""Initialize inputs. """

dut.nclk.value = 0
dut.scan_in.value = 0
dut.an_ac_scan_type_dc.value = 0x0
dut.an_ac_chipid_dc.value = 0x0
@ -62,7 +61,7 @@ async def init(dut, sim):
dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)

# why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
if sim.threads == 1:
if sim.a2o.config.threads == 1:
dut.an_ac_pm_thread_stop.value = 0x1
dut.an_ac_external_mchk.value = 0
dut.an_ac_sleep_en.value = 0
@ -72,7 +71,7 @@ async def init(dut, sim):
dut.an_ac_hang_pulse.value = 0
dut.an_ac_uncond_dbg_event.value = 0
else:
for i in range(sim.threads):
for i in range(sim.a2o.config.threads):
dut.an_ac_pm_thread_stop[i].value = 0x1
dut.an_ac_external_mchk[i].value = 0
dut.an_ac_sleep_en[i].value = 0
@ -105,27 +104,27 @@ async def config(dut, sim):
cpcr4_q = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_l2
cpcr4_act = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_wren

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if sim.config.core.creditsLd is not None:
creditsLd.value = Force(sim.config.core.creditsLd)
creditsLdMax.value = Force(sim.config.core.creditsLd)
sim.msg(f'A2L2: load credits changed from {creditsLd.value.integer} to {sim.config.core.creditsLd}.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
creditsLd.value = Release()

if sim.config.core.creditsSt is not None:
creditsSt.value = Force(sim.config.core.creditsSt)
creditsStMax.value = Force(sim.config.core.creditsSt)
sim.msg(f'A2L2: store credits changed from {creditsSt.value.integer} to {sim.config.core.creditsSt}.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
creditsSt.value = Release()

if sim.config.core.creditsLdStSingle is not None:
v = 1 if sim.config.core.creditsLdStSingle else 0
creditsLdStSingle.value = Force(v)
sim.msg(f'A2L2: only one load OR store allowed when credits=1/1.')
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
creditsLdStSingle.value = Release()

#wtf make a function - needs mask,thread
@ -136,7 +135,7 @@ async def config(dut, sim):
v = v << 2
v = (lsucr0_q.value.integer & ~0x4) | v
lsucr0_d.value = Force(v)
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
lsucr0_d.value = Release()
sim.msg(f'LSUCR0 = {hex(lsucr0_q.value), 8}')

@ -146,18 +145,17 @@ async def config(dut, sim):
sim.msg(f'Setting CPCR4[SQ_CNT] = {v}.')
v = v << 0
v = (cpcr4_q[0].value.integer & ~0x1F) | v
await RisingEdge(dut.clk_1x) # need cuz of act?
await RisingEdge(sim.sigClk) # need cuz of act?
cpcr4_d[0].value = Force(v)
cpcr4_act.value = Force(1)
await RisingEdge(dut.clk_1x)
await RisingEdge(dut.clk_1x) # need cuz of act?
await RisingEdge(sim.sigClk)
await RisingEdge(sim.sigClk) # need cuz of act?
cpcr4_d[0].value = Release()
cpcr4_act.value = Release()
sim.msg(f'CPCR4 = {hex(cpcr4_q[0], 8)}')

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
async def genReset(dut, sim):
"""Generate reset. """

@ -165,38 +163,37 @@ async def genReset(dut, sim):
done = False

while not done:
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
if sim.cycle < sim.resetCycle:
if first:
dut._log.info(f'[{sim.cycle:08d}] Resetting...')
first = False
dut.nclk[1].value = 1
sim.sigRst.value = 1
elif not done:
dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
dut.nclk[1].value = 0
sim.sigRst.value = 0
done = True
sim.resetDone = True

async def genClocks(dut, sim):
"""Generate 1x, 2x, 4x clock pulses, depending on parms. """

if sim.clk2x and sim.clk4x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
if sim.sigClk2x is not None and sim.sigClk4x is not None:
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
await cocotb.start(sim.clk2x.start())
sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
sim.clk4x = Clock(sim.sigClk4x, 2, 'ns')
await cocotb.start(sim.clk4x.start())
elif sim.clk2x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
elif sim.sigClk2x is not None:
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
await cocotb.start(sim.clk2x.start())
else:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())


for cycle in range(sim.maxCycles):

sim.cycle = cycle
@ -204,7 +201,7 @@ async def genClocks(dut, sim):
if cycle % sim.hbCycles == 0:
dut._log.info(f'[{cycle:08d}] ...tick...')

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
sim.ok = False
@ -225,6 +222,7 @@ async def scom(dut, sim):
# ------------------------------------------------------------------------------------------------
# Do something

# ************************************************************************************************
@cocotb.test()
async def tb(dut):
"""A Vulgar Display of OpenPower"""
@ -232,11 +230,21 @@ async def tb(dut):
sim = Sim(dut)
sim.mem = Memory(sim)
sim.maxCycles = 20000
sim.sigClk = dut.clk
sim.sigRst = dut.rst
sim.resetAddr = 0xFFFFFFFC
# original fpga design needed 4 cred, no fwd (set in logic currently)
#sim.config.core.creditsSt = 32
#sim.config.core.lsDataForward = 0 # disable=1
#sim.config.core.cpcr4_sq_cnt = 0 # default=6

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

'''
# rom
sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm
@ -318,19 +326,121 @@ async def tb(dut):
await cocotb.start(A2L2.monitor(dut, sim))

await Timer((sim.resetCycle + 5)*8, units='ns')
if dut.nclk[1].value != 0:
if sim.sigRst.value != 0:
sim.ok = False
sim.fail = 'Reset active too long!'

# config stuff
#await config(dut, sim)

# monitor stuff
#await cocotb.start(coreMonitor(dut, sim))

# release thread(s)
dut.an_ac_pm_thread_stop.value = 0
await RisingEdge(sim.sigClk)
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')

# what should this wait? genClocks?
await Timer((sim.maxCycles+100)*8, units='ns')

if sim.ok:
dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
else:
dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
assert False

# ************************************************************************************************
@cocotb.test()
async def tb_smt(dut):
"""A Vulgar Display of OpenPower"""

sim = Sim(dut)
sim.mem = Memory(sim)
sim.maxCycles = 20000
sim.sigClk = dut.clk
sim.sigRst = dut.rst
#t1 takes prot exc??? ierat 14 should be ok. set to 0 in tri_a2o.vh for now
#sim.resetAddr = 0xFFFFFFFC
#t1 starts but need more stuff; 2 printf buffers, etc.

# original fpga design needed 4 cred, no fwd (set in logic currently)
#sim.config.core.creditsSt = 32
#sim.config.core.lsDataForward = 0 # disable=1
#sim.config.core.cpcr4_sq_cnt = 0 # default=6

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.config.threads = 2
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

# rom+bios+arcitst
sim.memFiles = [
{
'addr': 0x00000000,
'file' : '../mem/test3/rom_smt.init'
}
]

'''
# rom+bios+dhrystone
sim.memFiles = [
{
'addr': 0x00000000,
'file' : '../mem/dhrystone/rom.init'
}
]
'''

for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])

if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
sim.mem.write(sim.resetAddr, sim.resetOp)
sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')

# init stuff
await init(dut, sim)

# start clocks,reset
await cocotb.start(genClocks(dut, sim))
await cocotb.start(genReset(dut, sim))

# start interfaces
await cocotb.start(scom(dut, sim))

sim.a2o = A2OCore(sim)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

await cocotb.start(A2O.driver(dut, sim))
await cocotb.start(A2O.checker(dut, sim))
await cocotb.start(A2O.monitor(dut, sim))

await cocotb.start(A2L2.driver(dut, sim))
await cocotb.start(A2L2.checker(dut, sim))
await cocotb.start(A2L2.monitor(dut, sim))

await Timer((sim.resetCycle + 5)*8, units='ns')
if sim.sigRst.value != 0:
sim.ok = False
sim.fail = 'Reset active too long!'

# config stuff
await config(dut, sim)
#await config(dut, sim)

# monitor stuff
#await cocotb.start(coreMonitor(dut, sim))

# release thread(s)
dut.an_ac_pm_thread_stop.value = 0
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')

# what should this wait? genClocks?

@ -23,7 +23,6 @@ from A2L2 import *
async def init(dut, sim):
"""Initialize inputs. """

dut.nclk.value = 0
dut.scan_in.value = 0
dut.an_ac_reset_1_complete.value = 0
dut.an_ac_reset_2_complete.value = 0
@ -64,9 +63,8 @@ async def init(dut, sim):
async def config(dut, sim):
"""Configure node, etc. """

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
async def genReset(dut, sim):
"""Generate reset. """

@ -74,35 +72,35 @@ async def genReset(dut, sim):
done = False

while not done:
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
if sim.cycle < sim.resetCycle:
if first:
dut._log.info(f'[{sim.cycle:08d}] Resetting...')
first = False
dut.nclk[1].value = 1
sim.sigRst.value = 1
elif not done:
dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
dut.nclk[1].value = 0
sim.sigRst.value = 0
done = True
sim.resetDone = True

async def genClocks(dut, sim):
"""Generate 1x, 2x, 4x clock pulses, depending on parms. """

if sim.clk2x and sim.clk4x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
if sim.sigClk2x is not None and sim.sigClk4x is not None:
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
await cocotb.start(sim.clk2x.start())
sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
sim.clk4x = Clock(sim.sigClk4x, 2, 'ns')
await cocotb.start(sim.clk4x.start())
elif sim.clk2x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
elif sim.sigClk2x is not None:
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
await cocotb.start(sim.clk2x.start())
else:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
sim.clk1x = Clock(sim.sigClk, 8, 'ns')
await cocotb.start(sim.clk1x.start())


@ -113,7 +111,7 @@ async def genClocks(dut, sim):
if cycle % sim.hbCycles == 0:
dut._log.info(f'[{cycle:08d}] ...tick...')

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
sim.ok = False
@ -128,7 +126,7 @@ async def memory(dut, sim):
sim.msg(f'{me}: started.')

while ok:
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

try:
addr = dut.mem_adr.value.integer
@ -168,7 +166,7 @@ async def checker(dut, sim):

while ok:

await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)

if not sim.resetDone:
continue
@ -200,6 +198,9 @@ async def tb_node(dut):
sim = Sim(dut)
sim.mem = Memory(sim)
sim.maxCycles = 20000
sim.sigClk = dut.clk
sim.sigRst = dut.rst
sim.resetAddr = 0xFFFFFFFC

'''
# rom
@ -240,6 +241,13 @@ async def tb_node(dut):
}
]

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])

@ -257,13 +265,6 @@ async def tb_node(dut):
# start interfaces
await cocotb.start(scom(dut, sim))

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

await cocotb.start(A2O.driver(dut, sim))

await cocotb.start(memory(dut, sim))
@ -272,14 +273,15 @@ async def tb_node(dut):
await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))

await Timer((sim.resetCycle + 5)*8, units='ns')
if dut.nclk[1].value != 0:
if sim.sigRst.value != 0:
sim.ok = False
sim.fail = 'Reset active too long!'

# config stuff

# config'd in tri_a2o.vh

# config for a2onode w/1 req buffer
# a2node_verilotor defines have these set already
#sim.a2o.config.creditsLd = 1
#sim.a2o.config.creditsSt = 1
#sim.a2o.config.creditsLdStSingle = True
@ -296,7 +298,7 @@ async def tb_node(dut):

# release thread(s)
dut.an_ac_pm_thread_stop.value = 0
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')

# should await sim.done
@ -317,6 +319,8 @@ async def tb_node_wb(dut):
sim = Sim(dut)
sim.mem = Memory(sim)
sim.maxCycles = 20000
sim.sigClk = dut.clk
sim.sigRst = dut.rst

# rom+bios+arcitst
sim.memFiles = [
@ -326,6 +330,13 @@ async def tb_node_wb(dut):
}
]

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])

@ -337,23 +348,14 @@ async def tb_node_wb(dut):
await init(dut, sim)

# start clocks,reset
await cocotb.start(genClocksLitex(dut, sim))
await cocotb.start(genResetLitex(dut, sim))
await cocotb.start(genClocks(dut, sim))
await cocotb.start(genReset(dut, sim))

# start interfaces
await cocotb.start(scom(dut, sim))

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

await cocotb.start(A2O.driver(dut, sim))

# sim memory
#await cocotb.start(memory(dut, sim))
# wishbone memory
from cocotbext.wishbone.monitor import WishboneSlave
# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
@ -367,7 +369,7 @@ async def tb_node_wb(dut):
"datrd": "wb_datr"
}
a2l2Iterable = A2L2Iterable()
wbs = WishboneSlave(dut, None, dut.clk_1x, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
A2L2.addWBSlave(dut, sim, wbSignals)
wbs.add_callback(A2L2.wbSlave)

@ -376,21 +378,10 @@ async def tb_node_wb(dut):
await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))

await Timer((sim.resetCycle + 5)*8, units='ns')
if dut.nclk[1].value != 0:
if sim.sigRst.value != 0:
sim.ok = False
sim.fail = 'Reset active too long!'

# config stuff

# config for a2onode w/1 req buffer
# a2node_verilator defines have these set already
#sim.a2o.config.creditsLd = 1
#sim.a2o.config.creditsSt = 1
#sim.a2o.config.creditsLdStSingle = True

# original fpga design needed 4 cred, no fwd (set in logic currently)
#sim.a2o.lsDataForward = 0 # disable=1

await A2O.config(dut, sim)

await cocotb.start(A2O.checker(dut, sim))
@ -400,7 +391,7 @@ async def tb_node_wb(dut):

# release thread(s)
dut.an_ac_pm_thread_stop.value = 0
await RisingEdge(dut.clk_1x)
await RisingEdge(sim.sigClk)
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')

# should await sim.done
@ -414,60 +405,16 @@ async def tb_node_wb(dut):
assert False

# ************************************************************************************************

# make these generic someday (sigs could be in sim, or passed in)
async def genResetLitex(dut, sim):
"""Generate reset. """

first = True
done = False

while not done:
await RisingEdge(dut.clk_1x)
if sim.cycle < sim.resetCycle:
if first:
dut._log.info(f'[{sim.cycle:08d}] Resetting...')
first = False
dut.rst.value = 1
elif not done:
dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
dut.rst.value = 0
done = True
sim.resetDone = True

async def genClocksLitex(dut, sim):
"""Generate 1x, 2x clock pulses, depending on parms. """

if sim.clk2x:
sim.clk1x = Clock(dut.clk_1x, 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.clk_2x, 4, 'ns')
await cocotb.start(sim.clk2x.start())
else:
sim.clk1x = Clock(dut.clk_1x, 8, 'ns')
await cocotb.start(sim.clk1x.start())

for cycle in range(sim.maxCycles):

sim.cycle = cycle

if cycle % sim.hbCycles == 0:
dut._log.info(f'[{cycle:08d}] ...tick...')

await RisingEdge(dut.clk_1x)

dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
sim.ok = False
sim.fail = 'Max cycle reached.'

@cocotb.test()
async def tb_litex(dut):
"""A2O wit litex interface"""
"""A2O with litex interface"""

sim = Sim(dut)
sim.mem = Memory(sim)
sim.maxCycles = 20000
sim.resetAddr = None # set to 00000000 in rtl define
sim.sigClk = dut.clk
sim.sigRst = dut.rst

# rom+bios+arcitst
sim.memFiles = [
@ -477,6 +424,17 @@ async def tb_litex(dut):
}
]

sim.config.a2l2 = DotMap({
'badAddr': [('E0','E0', 'IRW')]
})

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

for i in range(len(sim.memFiles)):
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])

@ -492,23 +450,14 @@ async def tb_litex(dut):
dut.cfg_wr.value = 0

# start clocks,reset
await cocotb.start(genClocksLitex(dut, sim))
await cocotb.start(genResetLitex(dut, sim))
await cocotb.start(genClocks(dut, sim))
await cocotb.start(genReset(dut, sim))

# start interfaces
await cocotb.start(scom(dut, sim))

sim.a2o = A2OCore(sim, dut.c0.c0)
sim.a2o.traceFacUpdates = True
sim.a2o.stopOnHang = 200
sim.a2o.stopOnLoop = 50
sim.a2o.iarPass = 0x7F0
sim.a2o.iarFail = 0x7F4

await cocotb.start(A2O.driver(dut, sim))

# sim memory
#await cocotb.start(memory(dut, sim))
# wishbone memory
from cocotbext.wishbone.monitor import WishboneSlave
# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
@ -522,7 +471,7 @@ async def tb_litex(dut):
"datrd": "wb_datr"
}
a2l2Iterable = A2L2Iterable()
wbs = WishboneSlave(dut, None, dut.clk_1x, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
A2L2.addWBSlave(dut, sim, wbSignals)
wbs.add_callback(A2L2.wbSlave)

@ -537,15 +486,6 @@ async def tb_litex(dut):

# config stuff

# config for a2onode w/1 req buffer
# a2node_verilator defines have these set already
#sim.a2o.config.creditsLd = 1
#sim.a2o.config.creditsSt = 1
#sim.a2o.config.creditsLdStSingle = True

# original fpga design needed 4 cred, no fwd (set in logic currently)
#sim.a2o.lsDataForward = 0 # disable=1

await A2O.config(dut, sim)

await cocotb.start(A2O.checker(dut, sim))

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