00001256 C0: CP 0:0001C0 00000000000001C0 1F44 is stw (lr) at orig stack + 4 - did it cross 64k? yeah 1F44/20004
00001262 C0: CP 0:0001C0 00000000000001C0
00001267 C0: CP 0:0001C0 00000000000001C0
00001272 C0: CP 0:0001C0 00000000000001C0
00001277 C0: CP 0:0001C0 00000000000001C0
00001280 C0: CP 0:0001C0 00000000000001C0
00001294 C0: CP 0:0001C0 00000000000001C0
00001308 C0: CP 0:0001C0 00000000000001C0
00001322 C0: CP 0:0001C0 00000000000001C0
00001336 C0: CP 0:0001C0 00000000000001C0
00001350 C0: CP 0:0001C0 00000000000001C0
*** Loop detected for 10 iterations ***
Quiescing...
00001366 C0: CP 0:0001C0 00000000000001C0
00001369 C0: CP 0:0001C0 00000000000001C0
tb_litex_soc
Cycles run=1376
You are worthless and weak.
```
* set top o stack to _fstack-8; now makes it through 4DF8 (in uart_init)...doh, need to add the derat entry for csr (memory_region,csr,0xfff00000,65536,io)
#### Core and wishbone wrapper with extra stuff for Litex integration
### Core and wishbone wrapper with extra stuff for Litex integration