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274 lines
9.2 KiB
Verilog
274 lines
9.2 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//-----------------------------------------------------------------------------------------------------
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// Title: rv_station12.vhdl
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// Desc: Parameterizable reservation station
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//-----------------------------------------------------------------------------------------------------
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module rv_barf(
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w0_dat,
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w0_addr,
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w0_en,
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w1_dat,
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w1_addr,
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w1_en,
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w_act,
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r0_addr,
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r0_dat,
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vdd,
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gnd,
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clk,
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rst,
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sg_1,
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func_sl_thold_1,
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ccflush_dc,
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act_dis,
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clkoff_b,
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d_mode,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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scan_in,
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scan_out
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);
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`include "tri_a2o.vh"
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parameter q_dat_width_g = 137;
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parameter q_num_entries_g = 16;
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parameter q_barf_enc_g=4;
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input [0:q_dat_width_g-1] w0_dat;
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input [0:q_barf_enc_g-1] w0_addr;
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input w0_en;
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input [0:q_dat_width_g-1] w1_dat;
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input [0:q_barf_enc_g-1] w1_addr;
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input w1_en;
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input [0:q_num_entries_g-1] w_act;
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input [0:q_barf_enc_g-1] r0_addr;
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output [0:q_dat_width_g-1] r0_dat;
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// pervasive
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inout vdd;
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inout gnd;
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input clk;
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input rst;
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input sg_1;
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input func_sl_thold_1;
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input ccflush_dc;
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input act_dis;
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input clkoff_b;
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input d_mode;
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input delay_lclkr;
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input mpw1_b;
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input mpw2_b;
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input scan_in;
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output scan_out;
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//-------------------------------------------------------------------------------------------------------
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// Type definitions
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//-------------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------------
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// Functions
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//-------------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Signals
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//-------------------------------------------------------------------
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wire [0:q_num_entries_g-1] sg_0;
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wire [0:q_num_entries_g-1] func_sl_thold_0;
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wire [0:q_num_entries_g-1] func_sl_thold_0_b;
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wire [0:q_num_entries_g-1] force_t;
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wire [0:q_num_entries_g-1] q_entry_load0;
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wire [0:q_num_entries_g-1] q_entry_load1;
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wire [0:q_num_entries_g-1] q_entry_hold;
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wire [0:q_num_entries_g-1] q_entry_read;
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wire [0:q_num_entries_g-1] q_read_dat[0:q_dat_width_g-1];
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wire [0:q_num_entries_g-1] q_dat_act;
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wire [0:q_dat_width_g-1] q_dat_d[0:q_num_entries_g-1];
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wire [0:q_dat_width_g-1] q_dat_q[0:q_num_entries_g-1];
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//-------------------------------------------------------------------
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// Scanchain
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//-------------------------------------------------------------------
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parameter q_dat_offset = 0;
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parameter scan_right = q_dat_offset + q_num_entries_g * q_dat_width_g;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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//-------------------------------------------------------------------------------------------------------
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// Notes
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//-------------------------------------------------------------------------------------------------------
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//
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//-------------------------------------------------------------------------------------------------------
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// misc
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//-------------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------------
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// Latch write data
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//-------------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------------
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// Write aoi
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//-------------------------------------------------------------------------------------------------------
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generate
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begin : xhdl1
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genvar n;
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for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
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begin : q_dat_gen
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wire [0:q_barf_enc_g-1] id= n;
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assign q_entry_load0[n] = (w0_addr == id) & w0_en;
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assign q_entry_load1[n] = (w1_addr == id) & w1_en;
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assign q_entry_hold[n] = (~q_entry_load0[n]) & (~q_entry_load1[n]);
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assign q_dat_d[n] = (w0_dat & {q_dat_width_g{q_entry_load0[n]}}) |
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(w1_dat & {q_dat_width_g{q_entry_load1[n]}}) |
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(q_dat_q[n] & {q_dat_width_g{q_entry_hold[n]}}); //feedback
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assign q_dat_act[n] = w_act[n];
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end
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end
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endgenerate
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//-------------------------------------------------------------------------------------------------------
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// Read Mux
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//-------------------------------------------------------------------------------------------------------
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generate
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begin : xhdl1r
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genvar n, b;
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for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
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begin : rgene
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wire [0:q_barf_enc_g-1] idd= n;
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//onehot addr
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assign q_entry_read[n] = (r0_addr == idd);
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for (b = 0; b <= (q_dat_width_g - 1); b = b + 1)
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begin : rgenb
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//AND
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assign q_read_dat[b][n] = q_dat_q[n][b] & q_entry_read[n];
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end
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end
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end
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endgenerate
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generate
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begin : xhdl1o
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genvar b;
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for (b = 0; b <= (q_dat_width_g - 1); b = b + 1)
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begin : rgeneo
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//OR
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assign r0_dat[b] = |(q_read_dat[b]);
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end
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end
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endgenerate
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//-------------------------------------------------------------------------------------------------------
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// storage elements
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//-------------------------------------------------------------------------------------------------------
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generate
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begin : xhdl2
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genvar n;
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for (n = 0; n <= q_num_entries_g - 1; n = n + 1)
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begin : q_x_q_gen
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tri_plat #(.WIDTH(2))
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perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(ccflush_dc),
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.din({func_sl_thold_1, sg_1}),
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.q({func_sl_thold_0[n], sg_0[n]})
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);
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tri_lcbor
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perv_lcbor(
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.clkoff_b(clkoff_b),
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.thold(func_sl_thold_0[n]),
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.sg(sg_0[n]),
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.act_dis(act_dis),
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.force_t(force_t[n]),
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.thold_b(func_sl_thold_0_b[n])
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);
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tri_rlmreg_p #(.WIDTH(q_dat_width_g), .INIT(0))
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q_dat_q_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(q_dat_act[n]),
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.thold_b(func_sl_thold_0_b[n]),
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.sg(sg_0[n]),
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.force_t(force_t[n]),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]),
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.scout(sov[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]),
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.din(q_dat_d[n]),
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.dout(q_dat_q[n])
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);
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end
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end
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endgenerate
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//---------------------------------------------------------------------
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// Scan
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//---------------------------------------------------------------------
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assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
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assign scan_out = sov[0];
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endmodule
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