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623 lines
26 KiB
Verilog
623 lines
26 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//********************************************************************
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//*
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//* TITLE: IU Microcode Buffers
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//*
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//* NAME: iuq_uc_buffer.v
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//*
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//*********************************************************************
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`include "tri_a2o.vh"
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module iuq_uc_buffer(
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vdd,
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gnd,
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nclk,
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pc_iu_func_sl_thold_0_b,
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pc_iu_sg_0,
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force_t,
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d_mode,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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scan_in,
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scan_out,
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iu3_val_l2,
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iu3_ifar_l2,
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iu3_2ucode_l2,
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iu3_0_instr_l2,
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iu3_1_instr_l2,
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iu3_2_instr_l2,
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iu3_3_instr_l2,
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ic_bp_iu2_flush,
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ic_bp_iu3_flush,
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ic_bp_iu3_ecc_err,
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bp_ib_iu3_val,
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uc_ib_iu3_invalid,
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uc_ib_iu3_flush_all,
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uc_ic_hold,
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uc_iu4_flush,
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uc_iu4_flush_ifar,
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xu_iu_flush,
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uc_val,
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advance_buffers,
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br_hold_l2,
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cplbuffer_full,
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clear_ill_flush_2ucode,
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next_valid,
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next_instr,
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iu2_flush,
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flush_next,
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flush_current
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);
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inout vdd;
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inout gnd;
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(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
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input [0:`NCLK_WIDTH-1] nclk;
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input pc_iu_func_sl_thold_0_b;
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input pc_iu_sg_0;
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input force_t;
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input d_mode;
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input delay_lclkr;
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input mpw1_b;
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input mpw2_b;
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(* pin_data ="PIN_FUNCTION=/SCAN_IN/" *)
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input scan_in;
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(* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *)
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output scan_out;
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input [0:3] iu3_val_l2;
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input [62-`EFF_IFAR_WIDTH:61] iu3_ifar_l2;
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input iu3_2ucode_l2; // Only iu3_0_instr0 can ever be 2ucode because xu_iu_flush clears everything before it.
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input [0:33] iu3_0_instr_l2;
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input [0:33] iu3_1_instr_l2;
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input [0:33] iu3_2_instr_l2;
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input [0:33] iu3_3_instr_l2;
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input ic_bp_iu2_flush;
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input ic_bp_iu3_flush;
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input ic_bp_iu3_ecc_err;
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input [0:3] bp_ib_iu3_val;
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output [0:3] uc_ib_iu3_invalid; // IB uses this to mask off the valids
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output uc_ib_iu3_flush_all; // IB uses this to clear buffer (because not enough time to get into iu3_invalid)
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output uc_ic_hold;
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output uc_iu4_flush;
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output [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar;
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input xu_iu_flush;
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// Internal to microcode
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input uc_val;
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input advance_buffers;
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input br_hold_l2;
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input cplbuffer_full;
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input clear_ill_flush_2ucode;
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output next_valid; // Does not include flush
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output [0:31] next_instr;
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output iu2_flush; // Does not include XU flush
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output flush_next; // Includes XU flush
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output flush_current; // Includes XU flush
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parameter uc_ic_hold_offset = 0;
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parameter uc_iu4_flush_offset = uc_ic_hold_offset + 1;
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parameter uc_iu4_flush_ifar_offset = uc_iu4_flush_offset + 1;
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parameter buffer_valid_offset = uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH;
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parameter buffer1_offset = buffer_valid_offset + 4; //buffer0_offset + 2;
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parameter buffer2_offset = buffer1_offset + 32;
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parameter buffer3_offset = buffer2_offset + 32;
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parameter buffer4_offset = buffer3_offset + 32;
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parameter scan_right = buffer4_offset + 32 - 1; //buffer_stg_iu4_offset + 5 - 1;
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// Latches
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wire uc_ic_hold_d;
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wire uc_iu4_flush_d;
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wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_d;
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wire [1:4] buffer_valid_d;
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wire [0:31] buffer1_d;
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wire [0:31] buffer2_d;
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wire [0:31] buffer3_d;
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wire [0:31] buffer4_d;
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wire uc_ic_hold_l2;
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wire uc_iu4_flush_l2;
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wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_l2;
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wire [1:4] buffer_valid_l2;
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wire [0:31] buffer1_l2;
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wire [0:31] buffer2_l2;
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wire [0:31] buffer3_l2;
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wire [0:31] buffer4_l2;
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wire [0:3] new_ucode_in;
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wire uc_buffer_act;
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wire uc_stall;
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// Left shift incoming microcode instructions
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wire [0:3] ucode_and_bp_in;
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wire [0:3] valid_in;
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wire [0:3] early_val_in;
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wire [0:31] instr0_in;
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wire [0:31] instr1_in;
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wire [0:31] instr2_in;
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wire [0:31] instr3_in;
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wire [60:61] ic_ifar0;
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wire [60:61] ic_ifar1;
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wire [60:61] ic_ifar2;
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wire [60:61] ic_ifar3;
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wire [60:61] ifar0_in;
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wire [60:61] ifar1_in;
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wire [60:61] ifar2_in;
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wire [60:61] ifar3_in;
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// Flushes
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wire iu3_flush;
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wire [0:3] early_need_flush_instr_in;
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wire [0:3] need_flush_instr_in;
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wire [60:61] overflow_flush_ifar;
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wire [0:3] imask0_in;
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wire [0:3] imask1_in;
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wire [0:3] imask2_in;
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wire [0:3] imask3_in;
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wire [0:3] uc_iu3_flush_imask;
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// Buffer
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wire bp_flush_next;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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//tidn <= '0';
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//tiup <= '1';
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assign new_ucode_in[0] = iu3_val_l2[0] & ((iu3_0_instr_l2[32:33] == 2'b01) | iu3_2ucode_l2);
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assign new_ucode_in[1] = iu3_val_l2[1] & (iu3_1_instr_l2[32:33] == 2'b01);
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assign new_ucode_in[2] = iu3_val_l2[2] & (iu3_2_instr_l2[32:33] == 2'b01);
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assign new_ucode_in[3] = iu3_val_l2[3] & (iu3_3_instr_l2[32:33] == 2'b01);
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// default act signal
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assign uc_buffer_act = uc_val | buffer_valid_l2[1] | (|(new_ucode_in)) | uc_iu4_flush_l2;
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// stall if processing command in buffer0 or commands are being held off. When current command finishes,
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// buffer0 takes next command when uc_end, but Buffers need to latch info
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// and advance next cycle because we cannot make timing (ib_uc_rdy comes late)
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// This means buffer0 can have same command as buffer1 for a cycle
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assign uc_stall = (uc_val | br_hold_l2 | cplbuffer_full) & (~advance_buffers);
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//---------------------------------------------------------------------
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// left shift incoming microcode instructions
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//---------------------------------------------------------------------
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//Detect if redirected by BP
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assign ucode_and_bp_in = new_ucode_in & bp_ib_iu3_val;
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assign valid_in[0] = |(ucode_and_bp_in);
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assign valid_in[1] = (~(( ucode_and_bp_in[0:2] == 3'b000) |
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(({ucode_and_bp_in[0:1], ucode_and_bp_in[3]}) == 3'b000) |
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(({ucode_and_bp_in[0], ucode_and_bp_in[2:3]}) == 3'b000) |
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( ucode_and_bp_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000
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assign valid_in[2] = ( ucode_and_bp_in[0:2] == 3'b111) |
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({ucode_and_bp_in[0:1], ucode_and_bp_in[3]} == 3'b111) |
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({ucode_and_bp_in[0], ucode_and_bp_in[2:3]} == 3'b111) |
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( ucode_and_bp_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111
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assign valid_in[3] = ucode_and_bp_in == 4'b1111;
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// This early signal does not include BP val, and is used for IB invalidate
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assign early_val_in[0] = |(new_ucode_in);
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assign early_val_in[1] = (~(( new_ucode_in[0:2] == 3'b000) |
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({new_ucode_in[0:1], new_ucode_in[3]} == 3'b000) |
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({new_ucode_in[0], new_ucode_in[2:3]} == 3'b000) |
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( new_ucode_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000
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assign early_val_in[2] = ( new_ucode_in[0:2] == 3'b111) |
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({new_ucode_in[0:1], new_ucode_in[3]} == 3'b111) |
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({new_ucode_in[0], new_ucode_in[2:3]} == 3'b111) |
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( new_ucode_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111
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assign early_val_in[3] = new_ucode_in == 4'b1111;
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assign instr0_in = (new_ucode_in[0] == 1'b1) ? iu3_0_instr_l2[0:31] : // 1---
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(new_ucode_in[1] == 1'b1) ? iu3_1_instr_l2[0:31] : // 01--
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(new_ucode_in[2] == 1'b1) ? iu3_2_instr_l2[0:31] : // 001-
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iu3_3_instr_l2[0:31];
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assign instr1_in = (new_ucode_in[0:1] == 2'b11) ? iu3_1_instr_l2[0:31] : // 11--
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(((new_ucode_in[0:2] == 3'b011) | // 011-
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(new_ucode_in[0:2] == 3'b101))) ? iu3_2_instr_l2[0:31] : // 101-
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iu3_3_instr_l2[0:31];
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assign instr2_in = (new_ucode_in[0:2] == 3'b111) ? iu3_2_instr_l2[0:31] : // 111-
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iu3_3_instr_l2[0:31];
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assign instr3_in = iu3_3_instr_l2[0:31];
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assign ic_ifar0 = iu3_ifar_l2[60:61];
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assign ic_ifar1 = (iu3_ifar_l2[60:61] == 2'b00) ? 2'b01 :
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(iu3_ifar_l2[60:61] == 2'b01) ? 2'b10 :
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2'b11;
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assign ic_ifar2 = {(~iu3_ifar_l2[60]), iu3_ifar_l2[61]};
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assign ic_ifar3 = 2'b11;
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assign ifar0_in = (new_ucode_in[0] == 1'b1) ? ic_ifar0 : // 1---
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(new_ucode_in[1] == 1'b1) ? ic_ifar1 : // 01--
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(new_ucode_in[2] == 1'b1) ? ic_ifar2 : // 001-
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ic_ifar3;
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assign ifar1_in = (new_ucode_in[0:1] == 2'b11) ? ic_ifar1 : // 11--
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(((new_ucode_in[0:2] == 3'b011) | // 011-
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(new_ucode_in[0:2] == 3'b101))) ? ic_ifar2 : // 101-
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ic_ifar3;
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assign ifar2_in = (new_ucode_in[0:2] == 3'b111) ? ic_ifar2 : // 111-
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ic_ifar3;
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assign ifar3_in = ic_ifar3;
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//---------------------------------------------------------------------
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// Flushes
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//---------------------------------------------------------------------
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// Does not include xu_iu_flush (for timing)
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assign iu3_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | ic_bp_iu3_ecc_err;
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assign iu2_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | (|(need_flush_instr_in)) | ic_bp_iu2_flush;
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// Need UC flush if overflowing buffer
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// early signal does not check BP val
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assign early_need_flush_instr_in = ((early_val_in[0] & buffer_valid_l2[4] & uc_stall) == 1'b1) ? 4'b1000 :
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((early_val_in[1] & ((buffer_valid_l2[3] & uc_stall) | (buffer_valid_l2[4] & (~uc_stall)))) == 1'b1) ? 4'b0100 :
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((early_val_in[2] & ((buffer_valid_l2[2] & uc_stall) | (buffer_valid_l2[3] & (~uc_stall)))) == 1'b1) ? 4'b0010 :
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((early_val_in[3] & ((buffer_valid_l2[1] & uc_stall) | (buffer_valid_l2[2] & (~uc_stall)))) == 1'b1) ? 4'b0001 :
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4'b0000;
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assign need_flush_instr_in = early_need_flush_instr_in & valid_in;
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assign overflow_flush_ifar[60:61] = (ifar0_in & {2{need_flush_instr_in[0]}}) |
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(ifar1_in & {2{need_flush_instr_in[1]}}) |
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(ifar2_in & {2{need_flush_instr_in[2]}}) |
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(ifar3_in & {2{need_flush_instr_in[3]}});
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assign uc_iu4_flush_ifar_d[62 - `EFF_IFAR_WIDTH:59] = iu3_ifar_l2[62 - `EFF_IFAR_WIDTH:59];
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assign uc_iu4_flush_ifar_d[60:61] = clear_ill_flush_2ucode ? ifar0_in :
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overflow_flush_ifar;
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// Which of the 4 instructions was flushed
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assign imask0_in = (new_ucode_in[0] == 1'b1) ? 4'b1111 : // 1---
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(new_ucode_in[1] == 1'b1) ? 4'b0111 : // 01--
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(new_ucode_in[2] == 1'b1) ? 4'b0011 : // 001-
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4'b0001;
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assign imask1_in = (new_ucode_in[0:1] == 2'b11) ? 4'b0111 : // 11--
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(((new_ucode_in[0:2] == 3'b011) | // 011-
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(new_ucode_in[0:2] == 3'b101))) ? 4'b0011 : // 101-
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4'b0001;
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assign imask2_in = (new_ucode_in[0:2] == 3'b111) ? 4'b0011 : // 111-
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4'b0001;
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assign imask3_in = 4'b0001;
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assign uc_iu3_flush_imask = (imask0_in & {4{early_need_flush_instr_in[0]}}) |
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(imask1_in & {4{early_need_flush_instr_in[1]}}) |
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(imask2_in & {4{early_need_flush_instr_in[2]}}) |
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(imask3_in & {4{early_need_flush_instr_in[3]}});
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assign uc_ib_iu3_invalid = uc_iu3_flush_imask | {4{uc_iu4_flush_l2}};
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assign uc_iu4_flush_d = (|(need_flush_instr_in) | clear_ill_flush_2ucode) & (~iu3_flush) & (~xu_iu_flush);
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assign uc_ib_iu3_flush_all = clear_ill_flush_2ucode & (~iu3_flush);
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// Detect IB flush
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// Simpler to wait until IU4 because BP flush is IU3 & IU4
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// (old)IB flush should take precedence over UC flush in IC because we invalidated UC flushes in IU3
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// UC flush should take precedence over BP flush in IC because we checked BP valids in IU3
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assign uc_iu4_flush = uc_iu4_flush_l2;
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assign uc_iu4_flush_ifar = uc_iu4_flush_ifar_l2;
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assign uc_ic_hold_d = (buffer_valid_d[4] == 1'b0) ? 1'b0 :
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(uc_iu4_flush_l2 == 1'b1) ? 1'b1 :
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uc_ic_hold_l2;
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assign uc_ic_hold = uc_ic_hold_l2;
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//---------------------------------------------------------------------
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// Buffers
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//---------------------------------------------------------------------
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// Buffer0 is the instruction that UC is currently working on
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assign next_instr = (buffer_valid_l2[2] == 1'b1 & advance_buffers == 1'b1) ? buffer2_l2[0:31] :
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(buffer_valid_l2[1] == 1'b1 & advance_buffers == 1'b0) ? buffer1_l2[0:31] :
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instr0_in;
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// Note: buffer0 could be taking buffer2 info next cycle, but we never can get an ib_flush on buffer0
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// in that scenario
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// ??? Do I want to switch ordering so bufferX_l2 is default case? (save power/toggling)
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assign buffer1_d = (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b1) ? buffer1_l2 :
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(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 :
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(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr1_in :
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instr0_in;
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assign buffer2_d = (uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 :
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(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 :
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|
(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr2_in :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr1_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr1_in :
|
|
instr0_in;
|
|
|
|
assign buffer3_d = (uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr3_in :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr2_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr2_in :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr1_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr1_in :
|
|
instr0_in;
|
|
|
|
assign buffer4_d = (uc_stall == 1'b1 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr3_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr3_in :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr2_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr2_in :
|
|
(uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b0) ? instr1_in :
|
|
(uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b0) ? instr1_in :
|
|
instr0_in;
|
|
|
|
// Output is never in IU4 now that we latch incoming IU2 signals
|
|
|
|
assign bp_flush_next = (|(new_ucode_in)) & (~valid_in[0]);
|
|
|
|
assign flush_current = xu_iu_flush; // Current instruction flushed
|
|
assign flush_next = ((~((buffer_valid_l2[2] & advance_buffers) | (buffer_valid_l2[1] & (~advance_buffers)))) & (iu3_flush | bp_flush_next)) | xu_iu_flush;
|
|
|
|
assign next_valid = (buffer_valid_l2[2] & advance_buffers) |
|
|
(buffer_valid_l2[1] & (~advance_buffers)) |
|
|
(|(new_ucode_in)); // Does not include flush
|
|
|
|
assign buffer_valid_d[1] = ((buffer_valid_l2[1] & uc_stall) |
|
|
buffer_valid_l2[2] |
|
|
(((valid_in[1]) |
|
|
(valid_in[0] & buffer_valid_l2[1]) |
|
|
(uc_stall & valid_in[0])) & (~iu3_flush)))
|
|
& (~xu_iu_flush);
|
|
|
|
assign buffer_valid_d[2] = ((buffer_valid_l2[2] & uc_stall) |
|
|
buffer_valid_l2[3] |
|
|
(((valid_in[2]) |
|
|
(valid_in[1] & buffer_valid_l2[1]) |
|
|
(valid_in[0] & buffer_valid_l2[2]) |
|
|
(uc_stall & (valid_in[1] |
|
|
(valid_in[0] & buffer_valid_l2[1])))) & (~iu3_flush)))
|
|
& (~xu_iu_flush);
|
|
|
|
assign buffer_valid_d[3] = ((buffer_valid_l2[3] & uc_stall) |
|
|
buffer_valid_l2[4] |
|
|
(((valid_in[3]) |
|
|
(valid_in[2] & buffer_valid_l2[1]) |
|
|
(valid_in[1] & buffer_valid_l2[2]) |
|
|
(valid_in[0] & buffer_valid_l2[3]) |
|
|
(uc_stall & (valid_in[2] |
|
|
(valid_in[1] & buffer_valid_l2[1]) |
|
|
(valid_in[0] & buffer_valid_l2[2])))) & (~iu3_flush)))
|
|
& (~xu_iu_flush);
|
|
|
|
assign buffer_valid_d[4] = ((buffer_valid_l2[4] & uc_stall) |
|
|
(((valid_in[3] & buffer_valid_l2[1]) |
|
|
(valid_in[2] & buffer_valid_l2[2]) |
|
|
(valid_in[1] & buffer_valid_l2[3]) |
|
|
(valid_in[0] & buffer_valid_l2[4]) |
|
|
(uc_stall & (valid_in[3] |
|
|
(valid_in[2] & buffer_valid_l2[1]) |
|
|
(valid_in[1] & buffer_valid_l2[2]) |
|
|
(valid_in[0] & buffer_valid_l2[3])))) & (~iu3_flush)))
|
|
& (~xu_iu_flush);
|
|
|
|
//---------------------------------------------------------------------
|
|
// Latches
|
|
//---------------------------------------------------------------------
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_ic_hold_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[uc_ic_hold_offset]),
|
|
.scout(sov[uc_ic_hold_offset]),
|
|
.din(uc_ic_hold_d),
|
|
.dout(uc_ic_hold_l2)
|
|
);
|
|
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_iu4_flush_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[uc_iu4_flush_offset]),
|
|
.scout(sov[uc_iu4_flush_offset]),
|
|
.din(uc_iu4_flush_d),
|
|
.dout(uc_iu4_flush_l2)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) uc_iu4_flush_ifar_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_iu4_flush_d),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]),
|
|
.scout(sov[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]),
|
|
.din(uc_iu4_flush_ifar_d),
|
|
.dout(uc_iu4_flush_ifar_l2)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) buffer_valid_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[buffer_valid_offset:buffer_valid_offset + 4 - 1]),
|
|
.scout(sov[buffer_valid_offset:buffer_valid_offset + 4 - 1]),
|
|
.din(buffer_valid_d),
|
|
.dout(buffer_valid_l2)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer1_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[buffer1_offset:buffer1_offset + 32 - 1]),
|
|
.scout(sov[buffer1_offset:buffer1_offset + 32 - 1]),
|
|
.din(buffer1_d),
|
|
.dout(buffer1_l2)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer2_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[buffer2_offset:buffer2_offset + 32 - 1]),
|
|
.scout(sov[buffer2_offset:buffer2_offset + 32 - 1]),
|
|
.din(buffer2_d),
|
|
.dout(buffer2_l2)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer3_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[buffer3_offset:buffer3_offset + 32 - 1]),
|
|
.scout(sov[buffer3_offset:buffer3_offset + 32 - 1]),
|
|
.din(buffer3_d),
|
|
.dout(buffer3_l2)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer4_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(uc_buffer_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[buffer4_offset:buffer4_offset + 32 - 1]),
|
|
.scout(sov[buffer4_offset:buffer4_offset + 32 - 1]),
|
|
.din(buffer4_d),
|
|
.dout(buffer4_l2)
|
|
);
|
|
|
|
//---------------------------------------------------------------------
|
|
// Scan
|
|
//---------------------------------------------------------------------
|
|
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
|
|
assign scan_out = sov[0];
|
|
|
|
endmodule
|