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867 lines
53 KiB
Plaintext
867 lines
53 KiB
Plaintext
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
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| Date : Wed Aug 3 07:40:26 2022
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| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
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| Command : report_timing_summary -file cmod7_timing_synth.rpt
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| Design : cmod7
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| Device : 7a200t-sbg484
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock (0)
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2. checking constant_clock (0)
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3. checking pulse_width_clock (0)
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4. checking unconstrained_internal_endpoints (828)
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5. checking no_input_delay (3)
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6. checking no_output_delay (3)
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7. checking multiple_clock (0)
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8. checking generated_clocks (0)
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9. checking loops (0)
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10. checking partial_input_delay (0)
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11. checking partial_output_delay (0)
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12. checking latch_loops (0)
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1. checking no_clock (0)
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------------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock (0)
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------------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock (0)
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---------------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints (828)
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--------------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 828 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)
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5. checking no_input_delay (3)
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------------------------------
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There are 3 input ports with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay (3)
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-------------------------------
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There are 3 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock (0)
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------------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks (0)
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--------------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops (0)
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---------------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay (0)
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------------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay (0)
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-------------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops (0)
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----------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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0.831 0.000 0 130983 0.011 0.000 0 130983 0.264 0.000 0 90094
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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clk12 {0.000 41.666} 83.333 12.000
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basesoc_mmcm_fb {0.000 41.666} 83.333 12.000
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crg_clkout0 {0.000 10.000} 20.000 50.000
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crg_clkout1 {0.000 5.000} 10.000 100.000
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crg_clkout2 {0.000 2.500} 5.000 200.001
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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clk12 82.121 0.000 0 7 0.150 0.000 0 7 16.667 0.000 0 10
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basesoc_mmcm_fb 16.667 0.000 0 2
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crg_clkout0 0.831 0.000 0 130696 0.011 0.000 0 130696 8.750 0.000 0 89885
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crg_clkout1 4.643 0.000 0 266 0.201 0.000 0 266 4.500 0.000 0 187
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crg_clkout2 0.885 0.000 0 14 0.011 0.000 0 14 0.264 0.000 0 10
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: clk12
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To Clock: clk12
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Setup : 0 Failing Endpoints, Worst Slack 82.121ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 82.121ns (required time - arrival time)
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Source: FDCE/C
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(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
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Destination: FDCE_1/D
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(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
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Path Group: clk12
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 83.333ns (clk12 rise@83.333ns - clk12 rise@0.000ns)
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Data Path Delay: 0.830ns (logic 0.496ns (59.759%) route 0.334ns (40.241%))
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Logic Levels: 0
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Clock Path Skew: -0.145ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 3.194ns = ( 86.527 - 83.333 )
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Source Clock Delay (SCD): 3.623ns
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Clock Pessimism Removal (CPR): 0.284ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk12 rise edge) 0.000 0.000 r
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0.000 0.000 r clk12 (IN)
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net (fo=0) 0.000 0.000 clk12
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IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
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net (fo=9, unplaced) 0.584 3.623 crg_clkin
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FDCE r FDCE/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.496 4.119 r FDCE/Q
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net (fo=1, unplaced) 0.334 4.453 basesoc_reset0
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FDCE r FDCE_1/D
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------------------------------------------------------------------- -------------------
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(clock clk12 rise edge) 83.333 83.333 r
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0.000 83.333 r clk12 (IN)
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net (fo=0) 0.000 83.333 clk12
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IBUF (Prop_ibuf_I_O) 1.365 84.698 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.760 85.458 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.091 85.549 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.439 85.988 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.100 86.088 r clk12_inst/O
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net (fo=9, unplaced) 0.439 86.527 crg_clkin
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FDCE r FDCE_1/C
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clock pessimism 0.284 86.811
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clock uncertainty -0.035 86.776
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FDCE (Setup_fdce_C_D) -0.202 86.574 FDCE_1
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-------------------------------------------------------------------
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required time 86.574
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arrival time -4.453
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-------------------------------------------------------------------
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slack 82.121
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Min Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.150ns (arrival time - required time)
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Source: FDCE/C
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(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
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Destination: FDCE_1/D
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(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
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Path Group: clk12
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (clk12 rise@0.000ns - clk12 rise@0.000ns)
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Data Path Delay: 0.299ns (logic 0.158ns (52.880%) route 0.141ns (47.120%))
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Logic Levels: 0
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): 1.349ns
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Source Clock Delay (SCD): 0.840ns
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Clock Pessimism Removal (CPR): 0.364ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk12 rise edge) 0.000 0.000 r
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0.000 0.000 r clk12 (IN)
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net (fo=0) 0.000 0.000 clk12
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IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
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net (fo=9, unplaced) 0.114 0.840 crg_clkin
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FDCE r FDCE/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.158 0.998 r FDCE/Q
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net (fo=1, unplaced) 0.141 1.139 basesoc_reset0
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FDCE r FDCE_1/D
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------------------------------------------------------------------- -------------------
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(clock clk12 rise edge) 0.000 0.000 r
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0.000 0.000 r clk12 (IN)
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net (fo=0) 0.000 0.000 clk12
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IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
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net (fo=9, unplaced) 0.259 1.349 crg_clkin
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FDCE r FDCE_1/C
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clock pessimism -0.364 0.985
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FDCE (Hold_fdce_C_D) 0.004 0.989 FDCE_1
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-------------------------------------------------------------------
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required time -0.989
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arrival time 1.139
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-------------------------------------------------------------------
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slack 0.150
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: clk12
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Waveform(ns): { 0.000 41.667 }
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Period(ns): 83.333
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Sources: { clk12 }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a BUFG/I n/a 2.155 83.333 81.178 clk12_IBUF_BUFG_inst/I
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Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 83.333 16.667 MMCME2_ADV/CLKIN1
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Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1
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High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1
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---------------------------------------------------------------------------------------------------
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From Clock: basesoc_mmcm_fb
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To Clock: basesoc_mmcm_fb
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: basesoc_mmcm_fb
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Waveform(ns): { 0.000 41.667 }
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Period(ns): 83.333
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Sources: { MMCME2_ADV/CLKFBOUT }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 83.333 82.084 MMCME2_ADV/CLKFBOUT
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Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 83.333 16.667 MMCME2_ADV/CLKFBIN
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---------------------------------------------------------------------------------------------------
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From Clock: crg_clkout0
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To Clock: crg_clkout0
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Setup : 0 Failing Endpoints, Worst Slack 0.831ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.831ns (required time - arrival time)
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Source: FDPE/C
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(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: FDPE_1/D
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(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: crg_clkout0
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 2.000ns (MaxDelay Path 2.000ns)
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Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
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Logic Levels: 0
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Clock Path Skew: -0.145ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.567ns
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Source Clock Delay (SCD): 5.191ns
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Clock Pessimism Removal (CPR): 0.479ns
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Clock Uncertainty: 0.300ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.597ns
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Phase Error (PE): 0.000ns
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Timing Exception: MaxDelay Path 2.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock crg_clkout0 rise edge)
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0.000 0.000 r
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0.000 0.000 r clk12 (IN)
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net (fo=0) 0.000 0.000 clk12
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IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
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net (fo=9, unplaced) 0.584 3.623 crg_clkin
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MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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0.088 3.711 r MMCME2_ADV/CLKOUT0
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net (fo=1, unplaced) 0.800 4.511 crg_clkout0
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BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG/O
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net (fo=89883, unplaced) 0.584 5.191 sys_clk
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FDPE r FDPE/C
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------------------------------------------------------------------- -------------------
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FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE/Q
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net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl0_rst_meta
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FDPE r FDPE_1/D
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------------------------------------------------------------------- -------------------
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max delay 2.000 2.000
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0.000 2.000 r clk12 (IN)
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net (fo=0) 0.000 2.000 clk12
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IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
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net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
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BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
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net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
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LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
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net (fo=9, unplaced) 0.439 5.194 crg_clkin
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MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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0.083 5.277 r MMCME2_ADV/CLKOUT0
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net (fo=1, unplaced) 0.760 6.037 crg_clkout0
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BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG/O
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net (fo=89883, unplaced) 0.439 6.567 sys_clk
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FDPE r FDPE_1/C
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clock pessimism 0.479 7.046
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clock uncertainty -0.300 6.745
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FDPE (Setup_fdpe_C_D) -0.067 6.678 FDPE_1
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-------------------------------------------------------------------
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required time 6.678
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arrival time -5.848
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-------------------------------------------------------------------
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slack 0.831
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Min Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.011ns (arrival time - required time)
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|
Source: FDPE/C
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: FDPE_1/D
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: crg_clkout0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (crg_clkout0 rise@0.000ns - crg_clkout0 rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.045ns
|
|
Source Clock Delay (SCD): 1.367ns
|
|
Clock Pessimism Removal (CPR): 0.533ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock crg_clkout0 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.114 0.840 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
0.050 0.890 r MMCME2_ADV/CLKOUT0
|
|
net (fo=1, unplaced) 0.337 1.227 crg_clkout0
|
|
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG/O
|
|
net (fo=89883, unplaced) 0.114 1.367 sys_clk
|
|
FDPE r FDPE/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE/Q
|
|
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl0_rst_meta
|
|
FDPE r FDPE_1/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock crg_clkout0 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.259 1.349 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
0.053 1.402 r MMCME2_ADV/CLKOUT0
|
|
net (fo=1, unplaced) 0.355 1.757 crg_clkout0
|
|
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG/O
|
|
net (fo=89883, unplaced) 0.259 2.045 sys_clk
|
|
FDPE r FDPE_1/C
|
|
clock pessimism -0.533 1.512
|
|
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_1
|
|
-------------------------------------------------------------------
|
|
required time -1.582
|
|
arrival time 1.593
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: crg_clkout0
|
|
Waveform(ns): { 0.000 10.000 }
|
|
Period(ns): 20.000
|
|
Sources: { MMCME2_ADV/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 a2owb/c0/lq0/ctl/dc32Kdir64B.arr/arr5_F/CLKARDCLK
|
|
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 20.000 193.360 MMCME2_ADV/CLKOUT0
|
|
Low Pulse Width Slow RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
|
|
High Pulse Width Fast RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: crg_clkout1
|
|
To Clock: crg_clkout1
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 4.643ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 4.643ns (required time - arrival time)
|
|
Source: a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
|
|
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
|
|
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: crg_clkout1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (crg_clkout1 rise@10.000ns - crg_clkout1 rise@0.000ns)
|
|
Data Path Delay: 4.203ns (logic 2.604ns (61.949%) route 1.599ns (38.051%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.567ns = ( 14.567 - 10.000 )
|
|
Source Clock Delay (SCD): 5.191ns
|
|
Clock Pessimism Removal (CPR): 0.479ns
|
|
Clock Uncertainty: 0.272ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.539ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock crg_clkout1 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.584 3.623 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
0.088 3.711 r MMCME2_ADV/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 4.511 crg_clkout1
|
|
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_1/O
|
|
net (fo=185, unplaced) 0.584 5.191 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
|
|
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
|
|
------------------------------------------------------------------- -------------------
|
|
RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[16])
|
|
2.454 7.645 r a2owb/c0/iuq0/bht2/bht0/bram0a/DOADO[16]
|
|
net (fo=1, unplaced) 0.800 8.445 a2owb/c0/iuq0/bht2/bht0/r_data_out_0_bram[20]
|
|
LUT2 (Prop_lut2_I0_O) 0.150 8.595 r a2owb/c0/iuq0/bht2/bht0/bram0a_i_17__1/O
|
|
net (fo=1, unplaced) 0.800 9.394 a2owb/c0/iuq0/bht2/bht0/w_data_in_0[15]
|
|
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock crg_clkout1 rise edge)
|
|
10.000 10.000 r
|
|
0.000 10.000 r clk12 (IN)
|
|
net (fo=0) 0.000 10.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 1.365 11.365 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.760 12.125 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.091 12.216 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.439 12.655 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.100 12.755 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.439 13.194 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
0.083 13.277 r MMCME2_ADV/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 14.037 crg_clkout1
|
|
BUFG (Prop_bufg_I_O) 0.091 14.128 r BUFG_1/O
|
|
net (fo=185, unplaced) 0.439 14.567 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
|
|
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
|
|
clock pessimism 0.479 15.046
|
|
clock uncertainty -0.272 14.774
|
|
RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[16])
|
|
-0.737 14.037 a2owb/c0/iuq0/bht2/bht0/bram0a
|
|
-------------------------------------------------------------------
|
|
required time 14.037
|
|
arrival time -9.394
|
|
-------------------------------------------------------------------
|
|
slack 4.643
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.201ns (arrival time - required time)
|
|
Source: a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
|
|
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
|
|
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: crg_clkout1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (crg_clkout1 rise@0.000ns - crg_clkout1 rise@0.000ns)
|
|
Data Path Delay: 0.437ns (logic 0.239ns (54.677%) route 0.198ns (45.323%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.045ns
|
|
Source Clock Delay (SCD): 1.367ns
|
|
Clock Pessimism Removal (CPR): 0.533ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock crg_clkout1 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.114 0.840 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
0.050 0.890 r MMCME2_ADV/CLKOUT1
|
|
net (fo=1, unplaced) 0.337 1.227 crg_clkout1
|
|
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_1/O
|
|
net (fo=185, unplaced) 0.114 1.367 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
|
|
FDRE r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.141 1.508 r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/Q
|
|
net (fo=1, unplaced) 0.198 1.706 a2owb/c0/iuq0/bht0/bht0/toggle2x_q
|
|
LUT2 (Prop_lut2_I0_O) 0.098 1.804 r a2owb/c0/iuq0/bht0/bht0/gate_fq_i_1__1/O
|
|
net (fo=1, unplaced) 0.000 1.804 a2owb/c0/iuq0/bht0/bht0/gate_d
|
|
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock crg_clkout1 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.259 1.349 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
0.053 1.402 r MMCME2_ADV/CLKOUT1
|
|
net (fo=1, unplaced) 0.355 1.757 crg_clkout1
|
|
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_1/O
|
|
net (fo=185, unplaced) 0.259 2.045 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
|
|
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/C
|
|
clock pessimism -0.533 1.512
|
|
FDRE (Hold_fdre_C_D) 0.091 1.603 a2owb/c0/iuq0/bht0/bht0/gate_fq_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.603
|
|
arrival time 1.804
|
|
-------------------------------------------------------------------
|
|
slack 0.201
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: crg_clkout1
|
|
Waveform(ns): { 0.000 5.000 }
|
|
Period(ns): 10.000
|
|
Sources: { MMCME2_ADV/CLKOUT1 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 10.000 7.424 a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
|
|
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 10.000 203.360 MMCME2_ADV/CLKOUT1
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: crg_clkout2
|
|
To Clock: crg_clkout2
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 0.885ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.885ns (required time - arrival time)
|
|
Source: FDPE_4/C
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
|
|
Destination: FDPE_5/D
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
|
|
Path Group: crg_clkout2
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 2.000ns (MaxDelay Path 2.000ns)
|
|
Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.567ns
|
|
Source Clock Delay (SCD): 5.191ns
|
|
Clock Pessimism Removal (CPR): 0.479ns
|
|
Clock Uncertainty: 0.246ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.487ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: MaxDelay Path 2.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock crg_clkout2 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.584 3.623 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
|
|
0.088 3.711 r MMCME2_ADV/CLKOUT2
|
|
net (fo=1, unplaced) 0.800 4.511 crg_clkout2
|
|
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_2/O
|
|
net (fo=8, unplaced) 0.584 5.191 idelay_clk
|
|
FDPE r FDPE_4/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE_4/Q
|
|
net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl2_rst_meta
|
|
FDPE r FDPE_5/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 2.000 2.000
|
|
0.000 2.000 r clk12 (IN)
|
|
net (fo=0) 0.000 2.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.439 5.194 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
|
|
0.083 5.277 r MMCME2_ADV/CLKOUT2
|
|
net (fo=1, unplaced) 0.760 6.037 crg_clkout2
|
|
BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG_2/O
|
|
net (fo=8, unplaced) 0.439 6.567 idelay_clk
|
|
FDPE r FDPE_5/C
|
|
clock pessimism 0.479 7.046
|
|
clock uncertainty -0.246 6.800
|
|
FDPE (Setup_fdpe_C_D) -0.067 6.733 FDPE_5
|
|
-------------------------------------------------------------------
|
|
required time 6.733
|
|
arrival time -5.848
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.011ns (arrival time - required time)
|
|
Source: FDPE_4/C
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
|
|
Destination: FDPE_5/D
|
|
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
|
|
Path Group: crg_clkout2
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (crg_clkout2 rise@0.000ns - crg_clkout2 rise@0.000ns)
|
|
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.045ns
|
|
Source Clock Delay (SCD): 1.367ns
|
|
Clock Pessimism Removal (CPR): 0.533ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock crg_clkout2 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.114 0.840 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
|
|
0.050 0.890 r MMCME2_ADV/CLKOUT2
|
|
net (fo=1, unplaced) 0.337 1.227 crg_clkout2
|
|
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_2/O
|
|
net (fo=8, unplaced) 0.114 1.367 idelay_clk
|
|
FDPE r FDPE_4/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE_4/Q
|
|
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl2_rst_meta
|
|
FDPE r FDPE_5/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock crg_clkout2 rise edge)
|
|
0.000 0.000 r
|
|
0.000 0.000 r clk12 (IN)
|
|
net (fo=0) 0.000 0.000 clk12
|
|
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
|
|
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
|
|
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
|
|
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
|
|
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
|
|
net (fo=9, unplaced) 0.259 1.349 crg_clkin
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
|
|
0.053 1.402 r MMCME2_ADV/CLKOUT2
|
|
net (fo=1, unplaced) 0.355 1.757 crg_clkout2
|
|
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_2/O
|
|
net (fo=8, unplaced) 0.259 2.045 idelay_clk
|
|
FDPE r FDPE_5/C
|
|
clock pessimism -0.533 1.512
|
|
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_5
|
|
-------------------------------------------------------------------
|
|
required time -1.582
|
|
arrival time 1.593
|
|
-------------------------------------------------------------------
|
|
slack 0.011
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: crg_clkout2
|
|
Waveform(ns): { 0.000 2.500 }
|
|
Period(ns): 5.000
|
|
Sources: { MMCME2_ADV/CLKOUT2 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL/REFCLK
|
|
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL/REFCLK
|
|
Low Pulse Width Fast FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C
|
|
High Pulse Width Slow FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C
|
|
|
|
|
|
|