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201 lines
8.0 KiB
Plaintext
201 lines
8.0 KiB
Plaintext
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
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| Date : Wed Aug 3 07:40:33 2022
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| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
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| Command : report_utilization -file cmod7_utilization_synth.rpt
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| Design : cmod7
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| Device : 7a200tsbg484-1
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| Design State : Synthesized
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------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+--------+-------+-----------+--------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+--------+-------+-----------+--------+
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| Slice LUTs* | 231525 | 0 | 134600 | 172.01 |
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| LUT as Logic | 230967 | 0 | 134600 | 171.60 |
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| LUT as Memory | 558 | 0 | 46200 | 1.21 |
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| LUT as Distributed RAM | 556 | 0 | | |
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| LUT as Shift Register | 2 | 0 | | |
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| Slice Registers | 89333 | 0 | 269200 | 33.18 |
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| Register as Flip Flop | 89333 | 0 | 269200 | 33.18 |
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| Register as Latch | 0 | 0 | 269200 | 0.00 |
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| F7 Muxes | 8148 | 0 | 67300 | 12.11 |
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| F8 Muxes | 3260 | 0 | 33650 | 9.69 |
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+----------------------------+--------+-------+-----------+--------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 4 | Yes | - | Set |
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| 8 | Yes | - | Reset |
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| 903 | Yes | Set | - |
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| 88418 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+-------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+-------+-------+-----------+-------+
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| Block RAM Tile | 101.5 | 0 | 365 | 27.81 |
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| RAMB36/FIFO* | 95 | 0 | 365 | 26.03 |
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| RAMB36E1 only | 95 | | | |
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| RAMB18 | 13 | 0 | 730 | 1.78 |
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| RAMB18E1 only | 13 | | | |
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+-------------------+-------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 740 | 0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB | 7 | 3 | 285 | 2.46 |
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| IOB Master Pads | 1 | | | |
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| IOB Slave Pads | 2 | | | |
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| Bonded IPADs | 0 | 0 | 14 | 0.00 |
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| Bonded OPADs | 0 | 0 | 8 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
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| PHASER_REF | 0 | 0 | 10 | 0.00 |
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| OUT_FIFO | 0 | 0 | 40 | 0.00 |
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| IN_FIFO | 0 | 0 | 40 | 0.00 |
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| IDELAYCTRL | 1 | 0 | 10 | 10.00 |
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| IBUFDS | 0 | 0 | 274 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
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| ILOGIC | 0 | 0 | 285 | 0.00 |
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| OLOGIC | 0 | 0 | 285 | 0.00 |
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+-----------------------------+------+-------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 4 | 0 | 32 | 12.50 |
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| BUFIO | 0 | 0 | 40 | 0.00 |
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| MMCME2_ADV | 1 | 0 | 10 | 10.00 |
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| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
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| BUFMRCE | 0 | 0 | 20 | 0.00 |
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| BUFHCE | 0 | 0 | 120 | 0.00 |
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| BUFR | 0 | 0 | 40 | 0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+------------+--------+---------------------+
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| Ref Name | Used | Functional Category |
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+------------+--------+---------------------+
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| LUT6 | 121905 | LUT |
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| FDRE | 88418 | Flop & Latch |
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| LUT5 | 62878 | LUT |
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| LUT4 | 40414 | LUT |
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| LUT3 | 14779 | LUT |
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| MUXF7 | 8148 | MuxFx |
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| LUT2 | 5981 | LUT |
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| MUXF8 | 3260 | MuxFx |
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| FDSE | 903 | Flop & Latch |
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| CARRY4 | 751 | CarryLogic |
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| RAMD64E | 540 | Distributed Memory |
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| LUT1 | 473 | LUT |
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| RAMB36E1 | 95 | Block Memory |
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| RAMD32 | 24 | Distributed Memory |
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| RAMB18E1 | 13 | Block Memory |
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| RAMS32 | 8 | Distributed Memory |
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| FDCE | 8 | Flop & Latch |
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| IBUF | 4 | IO |
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| FDPE | 4 | Flop & Latch |
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| BUFG | 4 | Clock |
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| OBUF | 3 | IO |
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| SRL16E | 2 | Distributed Memory |
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| MMCME2_ADV | 1 | Clock |
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| IDELAYCTRL | 1 | IO |
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+------------+--------+---------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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