a2o.py --csr-csv csr.csv
# completes OK and build/cmod7_kintex/software is created
32BE
a2o_32.py --csr-csv csr.csv
Running test binary command: /data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libc/meson-private/sanitycheckc.exe
C compiler for the build machine: ccache cc (gcc 9.4.0 "cc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0")
C linker for the build machine: cc ld.bfd 2.34
Build machine cpu family: x86_64
Build machine cpu: x86_64
Host machine cpu family: ppc
Host machine cpu: a2o
Target machine cpu family: ppc
Target machine cpu: a2o
../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/meson.build:99:2: ERROR: Problem encountered:
Unsupported architecture: "ppc"
change core.py cpu_family="powerpc"; warning only :)
Core and wishbone wrapper with extra stuff for Litex integration
create a2o/core.py and a2o.py (SOC) from a2p
makes it through vivado compile
cleaned up some various minor rtl warnings
added parm to cmod7 platform to allow replacing the target fpga device; trying arty-200 to see if it fits as-is - no, but can override?
ERROR: [DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 212846 of such cell types but only 134600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
try adding set drc.disableLUTOverUtilError 1 to build script and running...
cd build/cmod7/gateware
vivado -mode tcl -source cmod7.tcl
doesn't change results
try in gui:
set_property SEVERITY WARNING [get_drc_checks {DRC UTLZ-1}]
WARNING: [Vivado 12-4383] DRC UTLZ-1 may not change severity
do get the synth util report; iu=25% lq=28% xu=12% rv=16% fu=9% mmu=8%
4ed91f08a8