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503 lines
14 KiB
Python
503 lines
14 KiB
Python
# a2o test tb
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# a2owb with external sim mem interface
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import Timer
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from cocotb.triggers import FallingEdge
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from cocotb.handle import Force
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from cocotb.handle import Release
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import itertools
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from dotmap import DotMap
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from OPEnv import *
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from A2O import *
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from A2L2 import *
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# ------------------------------------------------------------------------------------------------
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# Tasks
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# get rid of z on anything that will be sampled here
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# is there a func to get all inputs?
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async def init(dut, sim):
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"""Initialize inputs. """
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dut.scan_in.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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dut.an_ac_reset_3_complete.value = 0
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dut.an_ac_reset_wd_complete.value = 0
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dut.an_ac_pm_fetch_halt.value = 0
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dut.an_ac_debug_stop.value = 0
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dut.an_ac_tb_update_enable.value = 1
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dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)
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# why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
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if sim.threads == 1:
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dut.an_ac_pm_thread_stop.value = 0x1
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dut.an_ac_external_mchk.value = 0
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dut.an_ac_sleep_en.value = 0
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dut.an_ac_ext_interrupt.value = 0
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dut.an_ac_crit_interrupt.value = 0
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dut.an_ac_perf_interrupt.value = 0
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dut.an_ac_hang_pulse.value = 0
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dut.an_ac_uncond_dbg_event.value = 0
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else:
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for i in range(sim.threads):
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dut.an_ac_pm_thread_stop[i].value = 0x1
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dut.an_ac_external_mchk[i].value = 0
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dut.an_ac_sleep_en[i].value = 0
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dut.an_ac_ext_interrupt[i].value = 0
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dut.an_ac_crit_interrupt[i].value = 0
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dut.an_ac_perf_interrupt[i].value = 0
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dut.an_ac_hang_pulse[i].value = 0
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dut.an_ac_uncond_dbg_event[i].value = 0
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dut.wb_datr = 0x08675309
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await Timer(9, units='ns')
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async def config(dut, sim):
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"""Configure node, etc. """
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await RisingEdge(sim.sigClk)
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async def genReset(dut, sim):
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"""Generate reset. """
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first = True
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done = False
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while not done:
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await RisingEdge(sim.sigClk)
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if sim.cycle < sim.resetCycle:
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if first:
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dut._log.info(f'[{sim.cycle:08d}] Resetting...')
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first = False
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sim.sigRst.value = 1
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elif not done:
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dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
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sim.sigRst.value = 0
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done = True
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sim.resetDone = True
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async def genClocks(dut, sim):
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"""Generate 1x, 2x, 4x clock pulses, depending on parms. """
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if sim.sigClk2x is not None and sim.sigClk4x is not None:
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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sim.clk4x = Clock(sim.sigClk4x, 2, 'ns')
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await cocotb.start(sim.clk4x.start())
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elif sim.sigClk2x is not None:
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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else:
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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for cycle in range(sim.maxCycles):
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sim.cycle = cycle
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if cycle % sim.hbCycles == 0:
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dut._log.info(f'[{cycle:08d}] ...tick...')
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
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sim.ok = False
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sim.fail = 'Max cycle reached.'
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# 16B interface
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async def memory(dut, sim):
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"""Handle external memory interface (BE)"""
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me = 'Memory'
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ok = True
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sim.msg(f'{me}: started.')
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while ok:
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await RisingEdge(sim.sigClk)
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try:
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addr = dut.mem_adr.value.integer
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w0 = sim.mem.read(addr)
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w1 = sim.mem.read(addr+4)
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w2 = sim.mem.read(addr+8)
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w3 = sim.mem.read(addr+12)
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v = cocotb.binary.BinaryValue()
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v.assign(f'{w0:0>32b}{w1:0>32b}{w2:0>32b}{w3:0>32b}')
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dut.mem_dat.value = v.value
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except Exception as e:
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#print(e)
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dut.mem_dat.value = 0
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if dut.mem_wr_val.value:
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addr = dut.mem_adr.value.integer & 0xFFFFFF0
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dat = hex(dut.mem_wr_dat, 32)
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be = f'{dut.mem_wr_be.value.integer:016b}'
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for i in range(4):
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sim.mem.write(addr, dat[i*8:i*8+8], be[i*4:i*4+4])
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addr += 4
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sim.msg(f'{me}: ended.')
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async def checker(dut, sim):
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"""Watch for error indicators"""
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me = 'Node Checker'
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ok = True
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sim.msg(f'{me}: started.')
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# errors
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nodeCheckstop = dut.an_ac_checkstop
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errors = [
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{'name': 'A2Node Checkstop', 'sig': nodeCheckstop}
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]
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while ok:
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await RisingEdge(sim.sigClk)
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if not sim.resetDone:
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continue
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for i in range(len(errors)):
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assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}'
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# ------------------------------------------------------------------------------------------------
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# Interfaces
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# SCOM
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async def scom(dut, sim):
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"""scom interface"""
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#dut.an_ac_scom_dch.value = 0
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#dut.an_ac_scom_cch.value = 0
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pass
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# ------------------------------------------------------------------------------------------------
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# Do something
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# ************************************************************************************************
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@cocotb.test()
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async def tb_node(dut):
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"""A Vulgar Display of OpenPower"""
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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sim.resetAddr = 0xFFFFFFFC
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'''
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# rom
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sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i])
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'''
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'''
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# rom+test; should end at 700
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test1/rom.init'
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},
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{
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'addr': 0x10000000,
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'file' : '../mem/test1/test.init'
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}
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]
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'''
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'''
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# rom+bios; should end at 7FC
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test2/rom.init'
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}
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]
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'''
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# rom+bios+arcitst
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test3/rom.init'
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}
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]
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
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sim.mem.write(sim.resetAddr, sim.resetOp)
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sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
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# init stuff
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await init(dut, sim)
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# start clocks,reset
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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await cocotb.start(A2O.driver(dut, sim))
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await cocotb.start(memory(dut, sim))
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#await cocotb.start(A2L2.driver(dut, sim))
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await cocotb.start(A2L2.checker(dut, sim))
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await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
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await Timer((sim.resetCycle + 5)*8, units='ns')
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if sim.sigRst.value != 0:
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sim.ok = False
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sim.fail = 'Reset active too long!'
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# config stuff
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# config'd in tri_a2o.vh
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# config for a2onode w/1 req buffer
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#sim.a2o.config.creditsLd = 1
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#sim.a2o.config.creditsSt = 1
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#sim.a2o.config.creditsLdStSingle = True
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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#sim.a2o.lsDataForward = 0 # disable=1
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await A2O.config(dut, sim)
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await cocotb.start(A2O.checker(dut, sim))
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await cocotb.start(A2O.monitor(dut, sim))
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await cocotb.start(checker(dut, sim))
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# release thread(s)
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dut.an_ac_pm_thread_stop.value = 0
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
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# should await sim.done
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await Timer((sim.maxCycles+100)*8, units='ns')
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if sim.ok:
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dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
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else:
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dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
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dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
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assert False
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# ************************************************************************************************
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@cocotb.test()
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async def tb_node_wb(dut):
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"""A2O with WB and cocoext slave"""
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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# rom+bios+arcitst
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test3/rom.init'
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}
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]
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
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sim.mem.write(sim.resetAddr, sim.resetOp)
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sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
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# init stuff
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await init(dut, sim)
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# start clocks,reset
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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await cocotb.start(A2O.driver(dut, sim))
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# wishbone memory
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from cocotbext.wishbone.monitor import WishboneSlave
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# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
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wbSignals = {"cyc": "wb_cyc",
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"stb": "wb_stb",
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"adr": "wb_adr",
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"we": "wb_we",
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"sel": "wb_sel",
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"datwr": "wb_datw",
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"ack": "wb_ack",
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"datrd": "wb_datr"
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}
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a2l2Iterable = A2L2Iterable()
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wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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A2L2.addWBSlave(dut, sim, wbSignals)
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wbs.add_callback(A2L2.wbSlave)
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#await cocotb.start(A2L2.driver(dut, sim))
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await cocotb.start(A2L2.checker(dut, sim))
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await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
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await Timer((sim.resetCycle + 5)*8, units='ns')
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if sim.sigRst.value != 0:
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sim.ok = False
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sim.fail = 'Reset active too long!'
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await A2O.config(dut, sim)
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await cocotb.start(A2O.checker(dut, sim))
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await cocotb.start(A2O.monitor(dut, sim))
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await cocotb.start(checker(dut, sim))
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# release thread(s)
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dut.an_ac_pm_thread_stop.value = 0
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
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# should await sim.done
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await Timer((sim.maxCycles+100)*8, units='ns')
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if sim.ok:
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dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
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else:
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dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
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dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
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assert False
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# ************************************************************************************************
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@cocotb.test()
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async def tb_litex(dut):
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"""A2O with litex interface"""
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.resetAddr = None # set to 00000000 in rtl define
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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# rom+bios+arcitst
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test3/rom.init'
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}
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]
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sim.config.a2l2 = DotMap({
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'badAddr': [('E0','E0', 'IRW')]
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})
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)):
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
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sim.mem.write(sim.resetAddr, sim.resetOp)
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sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
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# init stuff
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dut.externalInterrupt.value = 0
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dut.externalInterruptS.value = 0
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dut.timerInterrupt.value = 0
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dut.softwareInterrupt.value = 0
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dut.cfg_wr.value = 0
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# start clocks,reset
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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await cocotb.start(A2O.driver(dut, sim))
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# wishbone memory
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from cocotbext.wishbone.monitor import WishboneSlave
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# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
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wbSignals = {"cyc": "wb_cyc",
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"stb": "wb_stb",
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"adr": "wb_adr",
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"we": "wb_we",
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"sel": "wb_sel",
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"datwr": "wb_datw",
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"ack": "wb_ack",
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"datrd": "wb_datr"
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}
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a2l2Iterable = A2L2Iterable()
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wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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A2L2.addWBSlave(dut, sim, wbSignals)
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wbs.add_callback(A2L2.wbSlave)
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#await cocotb.start(A2L2.driver(dut, sim))
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await cocotb.start(A2L2.checker(dut, sim))
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await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
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await Timer((sim.resetCycle + 5)*8, units='ns')
|
|
if dut.rst.value != 0:
|
|
sim.ok = False
|
|
sim.fail = 'Reset active too long!'
|
|
|
|
# config stuff
|
|
|
|
await A2O.config(dut, sim)
|
|
|
|
await cocotb.start(A2O.checker(dut, sim))
|
|
await cocotb.start(A2O.monitor(dut, sim))
|
|
|
|
# should await sim.done
|
|
await Timer((sim.maxCycles+100)*8, units='ns')
|
|
|
|
if sim.ok:
|
|
dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
|
|
else:
|
|
dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
|
|
dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
|
|
assert False
|