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77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
`timescale 1 ps / 1 ps
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module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
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parameter bramAddrWidth = 9;
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parameter SIM_COLLISION_CHECK = "";
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output [7:0] DOA;
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output [7:0] DOB;
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output DOPA;
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output DOPB;
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input [10:0] ADDRA;
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input [10:0] ADDRB;
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input CLKA;
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input CLKB;
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input [7:0] DIA;
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input [7:0] DIB;
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input DIPA;
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input DIPB;
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input ENA;
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input ENB;
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input SSRA;
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input SSRB;
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input WEA;
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input WEB;
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wire [8:0] dina;
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wire [8:0] dinb;
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wire [8:0] douta;
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wire [8:0] doutb;
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wire [bramAddrWidth-1:0] bAddrA;
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wire [bramAddrWidth-1:0] bAddrB;
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wire unused;
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assign unused = |ADDRA[10:bramAddrWidth] | |ADDRB[10:bramAddrWidth];
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assign dina[8:0] = {DIPA, DIA[7:0]};
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assign dinb[8:0] = {DIPB, DIB[7:0]};
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assign DOA[7:0] = douta[7:0];
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assign DOPA = douta[8];
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assign DOB[7:0] = doutb[7:0];
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assign DOPB = doutb[8];
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assign bAddrA = ADDRA[(bramAddrWidth)-1:0];
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assign bAddrB = ADDRB[(bramAddrWidth)-1:0];
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generate if(1) begin
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genvar i;
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for (i = 0; i >= 0; i = i - 1) begin : ra
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bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(
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.DIA(dina[((i + 1) * 9) - 1:i * 9]),
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.DIB(dinb[((i + 1) * 9) - 1:i * 9]),
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.ADDRA(bAddrA),
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.ADDRB(bAddrB),
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.CLKA(CLKA),
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.CLKB(CLKB),
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.DOA(douta[((i + 1) * 9) - 1:i * 9]),
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.DOB(doutb[((i + 1) * 9) - 1:i * 9]),
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.SSRA(SSRA),
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.SSRB(SSRB),
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.WEA(WEA),
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.WEB(WEB),
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.ENA(ENA),
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.ENB(ENB)
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);
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end
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end
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endgenerate
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endmodule
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