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112 lines
3.3 KiB
Verilog
112 lines
3.3 KiB
Verilog
`timescale 1 ps / 1 ps
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module RAMB36(CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB,
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CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
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parameter bramAddrWidth = 10;
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parameter READ_WIDTH_A = 0;
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parameter READ_WIDTH_B = 0;
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parameter WRITE_WIDTH_A = 0;
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parameter WRITE_WIDTH_B = 0;
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parameter SIM_COLLISION_CHECK = "";
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parameter WRITE_MODE_A = "";
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parameter WRITE_MODE_B = "";
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output CASCADEOUTLATA;
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output CASCADEOUTLATB;
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output CASCADEOUTREGA;
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output CASCADEOUTREGB;
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output [31:0] DOA;
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output [31:0] DOB;
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output [3:0] DOPA;
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output [3:0] DOPB;
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input [15:0] ADDRA;
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input [15:0] ADDRB;
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input CASCADEINLATA;
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input CASCADEINLATB;
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input CASCADEINREGA;
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input CASCADEINREGB;
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input CLKA;
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input CLKB;
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input [31:0] DIA;
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input [31:0] DIB;
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input [3:0] DIPA;
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input [3:0] DIPB;
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input ENA;
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input ENB;
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input REGCEA;
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input REGCEB;
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input SSRA;
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input SSRB;
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input [3:0] WEA;
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input [3:0] WEB;
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wire [35:0] dina;
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wire [35:0] dinb;
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wire [35:0] douta;
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wire [35:0] doutb;
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wire [bramAddrWidth-1:0] bAddrA;
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wire [bramAddrWidth-1:0] bAddrB;
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wire unused;
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assign dina[35:27] = {DIPA[3], DIA[31:24]};
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assign dina[26:18] = {DIPA[2], DIA[23:16]};
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assign dina[17:9] = {DIPA[1], DIA[15:8]};
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assign dina[8:0] = {DIPA[0], DIA[7:0]};
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assign dinb[35:27] = {DIPB[3], DIB[31:24]};
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assign dinb[26:18] = {DIPB[2], DIB[23:16]};
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assign dinb[17:9] = {DIPB[1], DIB[15:8]};
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assign dinb[8:0] = {DIPB[0], DIB[7:0]};
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assign DOA[31:24] = douta[34:27];
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assign DOA[23:16] = douta[25:18];
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assign DOA[15:8] = douta[16:9];
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assign DOA[7:0] = douta[7:0];
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assign DOPA[3:0] = {douta[35], douta[26], douta[17], douta[8]};
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assign DOB[31:24] = doutb[34:27];
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assign DOB[23:16] = doutb[25:18];
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assign DOB[15:8] = doutb[16:9];
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assign DOB[7:0] = doutb[7:0];
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assign DOPB[3:0] = {doutb[35], doutb[26], doutb[17], doutb[8]};
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assign bAddrA = ADDRA[(bramAddrWidth+5)-1:5];
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assign bAddrB = ADDRB[(bramAddrWidth+5)-1:5];
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generate if(1) begin
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genvar i;
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for (i = 3; i >= 0; i = i - 1) begin: ra
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bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(
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.DIA(dina[((i + 1) * 9) - 1:i * 9]),
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.DIB(dinb[((i + 1) * 9) - 1:i * 9]),
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.ADDRA(bAddrA),
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.ADDRB(bAddrB),
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.CLKA(CLKA),
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.CLKB(CLKB),
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.DOA(douta[((i + 1) * 9) - 1:i * 9]),
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.DOB(doutb[((i + 1) * 9) - 1:i * 9]),
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.SSRA(SSRA),
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.SSRB(SSRB),
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.WEA(WEA[i]),
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.WEB(WEB[i]),
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.ENA(ENA),
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.ENB(ENB)
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);
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end
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end
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endgenerate
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assign CASCADEOUTLATA = 1'b0;
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assign CASCADEOUTLATB = 1'b0;
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assign CASCADEOUTREGA = 1'b0;
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assign CASCADEOUTREGB = 1'b0;
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assign unused = CASCADEINLATA | CASCADEINLATB | CASCADEINREGA | CASCADEINREGB | |ADDRA[15:14] | |ADDRA[4:0] | |ADDRB[15:14] | |ADDRB[4:0] | REGCEA | REGCEB;
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endmodule
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