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125 lines
4.6 KiB
Verilog
125 lines
4.6 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_nlat.v
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// *! DESCRIPTION : Basic n-bit latch w/ internal scan
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_nlat(
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vd,
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gd,
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d1clk,
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d2clk,
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clk,
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rst,
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scan_in,
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din,
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q,
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q_b,
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scan_out
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);
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parameter OFFSET = 0;
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parameter SCAN = 0; //SCAN = normal;
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//0=normal,1=interleaved,2=reversed,3=reverse_interleaved
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parameter RESET_INVERTS_SCAN = 1'b1;
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parameter WIDTH = 1;
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parameter INIT = 0;
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parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
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//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
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parameter SYNTHCLONEDLATCH = "";
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parameter NEEDS_SRESET = 1; // for inferred latches
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parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs)
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inout vd;
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inout gd;
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input d1clk;
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input d2clk;
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input clk;
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input rst;
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input scan_in;
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input [OFFSET:OFFSET+WIDTH-1] din;
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output [OFFSET:OFFSET+WIDTH-1] q;
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output [OFFSET:OFFSET+WIDTH-1] q_b;
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output scan_out;
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// tri_nlat
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parameter [0:WIDTH-1] init_v = INIT;
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generate
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begin
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wire sreset;
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wire [0:WIDTH-1] int_din;
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reg [0:WIDTH-1] int_dout;
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wire [0:WIDTH-1] vact;
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wire [0:WIDTH-1] vact_b;
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wire [0:WIDTH-1] vsreset;
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wire [0:WIDTH-1] vsreset_b;
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wire [0:WIDTH-1] vthold;
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wire [0:WIDTH-1] vthold_b;
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(* analysis_not_referenced="true" *)
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wire unused;
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if (NEEDS_SRESET == 1) begin
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assign sreset = rst;
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end else begin
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assign sreset = 1'b0;
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end
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assign vsreset = {WIDTH{sreset}};
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assign vsreset_b = {WIDTH{~sreset}};
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assign int_din = (vsreset_b & din) | (vsreset & init_v);
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assign vact = {WIDTH{d1clk}};
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assign vact_b = {WIDTH{~d1clk}};
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assign vthold_b = {WIDTH{d2clk}};
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assign vthold = {WIDTH{~d2clk}};
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always @(posedge clk) begin: l
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//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
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if (sreset)
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int_dout <= int_din;
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else if (d1clk & d2clk)
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int_dout <= int_din;
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end
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assign q = int_dout;
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assign q_b = (~int_dout);
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assign scan_out = 1'b0;
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assign unused = | {vd, gd, scan_in};
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end
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endgenerate
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endmodule
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