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173 lines
7.0 KiB
Python
173 lines
7.0 KiB
Python
#wtf from litex-boards; added some stuff from https://github.com/litex-hub/fpga_101
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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('clk12', 0, Pins('L17'), IOStandard('LVCMOS33')),
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# Leds
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('user_led', 0, Pins('A17'), IOStandard('LVCMOS33')), # LD1
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('user_led', 1, Pins('C16'), IOStandard('LVCMOS33')), # LD2
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# RGB
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('user_rgb_led', 0,
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Subsignal('r', Pins('C17')),
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Subsignal('g', Pins('B16')),
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Subsignal('b', Pins('B17')),
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IOStandard('LVCMOS33'),
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),
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# Buttons
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('user_btn', 0, Pins('A18'), IOStandard('LVCMOS33')), # B0
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('user_btn', 1, Pins('B18'), IOStandard('LVCMOS33')), # B1
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#### test to see if can add uart by changing platform
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('uart_0', 0,
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Subsignal('tx', Pins('J3')), # 10
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Subsignal('rx', Pins('J1')), # 11
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IOStandard('LVCMOS33'),
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),
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# GPIO
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('digital', 0, Pins('M3'), IOStandard('LVCMOS33')), # 1
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('digital', 1, Pins('L3'), IOStandard('LVCMOS33')), # 2
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('digital', 2, Pins('A16'), IOStandard('LVCMOS33')), # 3
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('digital', 3, Pins('K3'), IOStandard('LVCMOS33')), # 4
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('digital', 4, Pins('C15'), IOStandard('LVCMOS33')), # 5
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('digital', 5, Pins('H1'), IOStandard('LVCMOS33')), # 6
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('digital', 6, Pins('A15'), IOStandard('LVCMOS33')), # 7
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('digital', 7, Pins('B15'), IOStandard('LVCMOS33')), # 8
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('digital', 8, Pins('A14'), IOStandard('LVCMOS33')), # 9
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('digital', 9, Pins('J3'), IOStandard('LVCMOS33')), # 10
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('digital', 10, Pins('J1'), IOStandard('LVCMOS33')), # 11
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('digital', 11, Pins('K2'), IOStandard('LVCMOS33')), # 12
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('digital', 12, Pins('L1'), IOStandard('LVCMOS33')), # 13
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('digital', 13, Pins('L2'), IOStandard('LVCMOS33')), # 14
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('digital', 14, Pins('M1'), IOStandard('LVCMOS33')), # 17
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('digital', 15, Pins('N3'), IOStandard('LVCMOS33')), # 18
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('digital', 16, Pins('P3'), IOStandard('LVCMOS33')), # 19
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('digital', 17, Pins('M2'), IOStandard('LVCMOS33')), # 20
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('digital', 18, Pins('N1'), IOStandard('LVCMOS33')), # 21
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('digital', 19, Pins('N2'), IOStandard('LVCMOS33')), # 22
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('digital', 20, Pins('P1'), IOStandard('LVCMOS33')), # 23
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('digital', 21, Pins('R3'), IOStandard('LVCMOS33')), # 26
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('digital', 22, Pins('T3'), IOStandard('LVCMOS33')), # 27
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('digital', 23, Pins('R2'), IOStandard('LVCMOS33')), # 28
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('digital', 24, Pins('T1'), IOStandard('LVCMOS33')), # 29
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('digital', 25, Pins('T2'), IOStandard('LVCMOS33')), # 30
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('digital', 26, Pins('U1'), IOStandard('LVCMOS33')), # 31
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('digital', 27, Pins('W2'), IOStandard('LVCMOS33')), # 32
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('digital', 28, Pins('V2'), IOStandard('LVCMOS33')), # 33
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('digital', 29, Pins('W3'), IOStandard('LVCMOS33')), # 34
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('digital', 30, Pins('V3'), IOStandard('LVCMOS33')), # 35
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('digital', 31, Pins('W5'), IOStandard('LVCMOS33')), # 36
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('digital', 32, Pins('V4'), IOStandard('LVCMOS33')), # 37
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('digital', 33, Pins('U4'), IOStandard('LVCMOS33')), # 38
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('digital', 34, Pins('V5'), IOStandard('LVCMOS33')), # 39
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('digital', 35, Pins('W4'), IOStandard('LVCMOS33')), # 40
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('digital', 36, Pins('U5'), IOStandard('LVCMOS33')), # 41
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('digital', 37, Pins('U2'), IOStandard('LVCMOS33')), # 42
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('digital', 38, Pins('W6'), IOStandard('LVCMOS33')), # 43
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('digital', 39, Pins('U3'), IOStandard('LVCMOS33')), # 44
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('digital', 40, Pins('U7'), IOStandard('LVCMOS33')), # 45
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('digital', 41, Pins('W7'), IOStandard('LVCMOS33')), # 46
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('digital', 42, Pins('U8'), IOStandard('LVCMOS33')), # 47
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('digital', 43, Pins('V8'), IOStandard('LVCMOS33')), # 48
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# declare these to use GPIO 15/16 as analog to xadc
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('analog', 0,
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Subsignal('n'), Pins('G2'),
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Subsignal('p'), Pins('G3'),
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IOStandard('LVCMOS33')
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),
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('analog', 1,
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Subsignal('n'), Pins('J2'),
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Subsignal('p'), Pins('H2'),
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IOStandard('LVCMOS33')
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),
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# PMOD
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('pmod', 0, Pins('G17'), IOStandard('LVCMOS33')), # 1
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('pmod', 1, Pins('G19'), IOStandard('LVCMOS33')), # 2
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('pmod', 2, Pins('N18'), IOStandard('LVCMOS33')), # 3
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('pmod', 3, Pins('L18'), IOStandard('LVCMOS33')), # 4
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('pmod', 4, Pins('H17'), IOStandard('LVCMOS33')), # 7
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('pmod', 5, Pins('H19'), IOStandard('LVCMOS33')), # 8
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('pmod', 6, Pins('J19'), IOStandard('LVCMOS33')), # 9
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('pmod', 7, Pins('K18'), IOStandard('LVCMOS33')), # 10
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# Serial
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('serial', 0,
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Subsignal('tx', Pins('J18')),
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Subsignal('rx', Pins('J17')),
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IOStandard('LVCMOS33'),
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),
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# JTAG: TMS(W9),TCK(C8),TDI(W10),TDO(W8)
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# Crypto 1-Wire (?) - goes to ATSHA204A-MAHCZ-T
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('crypto_sda', 0, Pins('D17'), IOStandard('LVCMOS33')),
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# QSPI
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('mx25l3233_spi', 0,
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Subsignal('cs', Pins('K19')),
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Subsignal('mosi', Pins('D18')), # DQ0
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Subsignal('miso', Pins('D19')), # DQ1
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#Subsignal('clk', Pins('E19')), # ref says E19; doesn't show in xdc; C11 in schematic
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# ref: On other boards, SCK is an exception because it remains a dedicated pin even after configuration,
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# however, on the Cmod A7 the SCK signal is routed to an additional general purpose pin that can be
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# accessed after configuration (pin E19). This allows access to this pin without having to instantiate
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# the special FPGA primitive called STARTUPE2.
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Subsignal('wp', Pins('G18')), # DQ2
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Subsignal('hld', Pins('F18')), # DQ3
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IOStandard('LVCMOS33')
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),
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# SRAM
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('issiram', 0,
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Subsignal('addr', Pins('M18 M19 K17 N17 P17 P18 R18 W19 U19 V19 W18 T17 T18 U17 U18 V16 W16 W17 V15'),
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IOStandard('LVCMOS33')
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),
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Subsignal('data', Pins('W15 W13 W14 U15 U16 V13 V14 U14'),
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IOStandard('LVCMOS33')
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),
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#this shows up as input! issiram_oen
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Subsignal('oen', Pins('P19'), IOStandard('LVCMOS33')),
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Subsignal('wen', Pins('R19'), IOStandard('LVCMOS33')),
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Subsignal('cen', Pins('N19'), IOStandard('LVCMOS33')),
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Misc('SLEW=FAST')
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = 'clk12'
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default_clk_period = 1e9/12e6
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def __init__(self, fpga=None):
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if fpga is None: # real cmod7
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XilinxPlatform.__init__(self, 'xc7a35t-CPG236-1', _io, toolchain='vivado')
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else: # phony for build
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XilinxPlatform.__init__(self, fpga, _io, toolchain='vivado')
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#def create_programmer(self):
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# return OpenOCD('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a100t.bit')
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request('clk12', loose=True), self.default_clk_period)
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