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224 lines
8.6 KiB
Python
224 lines
8.6 KiB
Python
#!/usr/bin/python3
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# A2O Test (64LE)
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# a2o.py --csr-csv csr.csv --no-compile-software
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# a2o.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6]
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#
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import os
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import argparse
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from migen import *
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# wtf - use local platform
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from platforms import cmod7
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from platforms import cmod7_kintex
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# wtf - use local core (not built into litex)
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# help python find package
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# not needed anymore
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#import sys
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#binPath = os.path.dirname(os.path.realpath(__file__))
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#sys.path.append(os.path.join(binPath, 'a2o')) # dir with core package; core.py defines core source location
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# get core def
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from a2o import A2O
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# add to litex dict
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from litex.soc.cores import cpu
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cpu.CPUS['a2o'] = A2O
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.interconnect import wishbone
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from litex.soc.cores import uart
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from litex.soc.cores.uart import UART
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from litex.soc.cores.uart import UARTPHY
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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#wtf how do you add btn to reset sig?
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#x = platform.request('user_btn',0)
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self.comb += pll.reset.eq(self.rst)
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#self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request('clk12'), 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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def _to_signal(obj):
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return obj.raw_bits() if isinstance(obj, Record) else obj
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6),
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with_analyzer=False,
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uart_baudrate=115200,
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**kwargs):
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coreUART = True
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#romSize = 128*1024
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#ramSize = 128*1024
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romSize = 64 * 1024;
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ramSize = 64 * 1024;
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ddrSize = 16*1024*1024
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# try build using different fpga's
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#platform = cmod7.Platform()
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#platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
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#platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 ) # kintex-325
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platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1') # kintex-410
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SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
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#with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!!
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with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0,
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ident='A2O', ident_version=True, uart_baudrate=uart_baudrate,
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cpu_type='a2o')
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print(f'Building variant={self.cpu.variant}.')
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# no irq yet, but should be able to connect; need irq handler in crt0.s
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self.add_constant('UART_POLLING')
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# this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
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#SoCCore.csr_map
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#self.csr_map = {**SoCCore.csr_map, **{
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#self.csr_map = {
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# 'ctrl': 0,
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# 'dna' : 1,
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# 'uart': 2,
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# 'i2c': 3,
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# 'leds': 4
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#}}
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#interrupt_map = {**soc_cls.interrupt_map, **{
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# 'uart': 0,
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# 'timer0': 1,
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#}}
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self.mem_map = {
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'rom': 0x00000000,
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'ram': 0x00010000,
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'main_ram': 0x01000000,
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'csr': 0xFFF00000
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}
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if not coreUART:
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self.submodules.serial_bridge = UARTWishboneBridge(platform.request('serial'), sys_clk_freq)
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self.add_wb_master(self.serial_bridge.wishbone)
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self.add_csr('node_ctl')
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self.add_csr('node_config')
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self.add_csr('node_status')
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# ON-BOARD MEM ------------------------------------------------------------------------------
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with open('rom.init', 'r') as file:
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hexdata = file.read().replace('\n', '')
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#a2o how will this work for a2o? should allow 32BE or 64LE to load kernel+bios
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# 1. core resets to 32BE
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# 2. probably want to link kernel+bios in same mode, so have kernel deal with possible mode switch
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# 3. load mem here in proper mode based on variant (A2O_32BE or A2O64_LE)
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outFile = open('mem_init', 'w') # write data immediately so available even if not building (sim)
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# this seems to work (specified in BE in rom.init, instructions are decoded properly)
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# BUT, vivado wants each line to be 4B to match width (at least for sim)
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bytedata = []
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for i in range(0, len(hexdata), 8):
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data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
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bytedata.append(data)
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outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
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#bytedata.append(int(hexdata[i:i+2] + hexdata[i+2:i+4] + hexdata[i+4:i+6] + hexdata[i+6:i+8], 16))
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romdata = bytedata
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print('Read ' + str(len(romdata)) + ' bytes for ROM data.')
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outFile.close()
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print('Wrote mem.init')
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self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata) # name, origin, size, contents=[], mode='r'
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# make this sram to match what linker expects
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self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize) # name, origin, size, contents=[], mode='rw'
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# External Mem -----------------------------------------------------------------------------
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self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all('user_led'),
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sys_clk_freq = sys_clk_freq
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)
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self.add_csr('leds')
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# Buttons
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self.submodules.buttons = GPIOIn(
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pads = platform.request_all('user_btn')
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)
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self.add_csr('buttons')
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# Analyzer ---------------------------------------------------------------------------------
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if with_analyzer:
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analyzer_signals = [
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self.cpu.wb_stb,
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self.cpu.wb_cyc,
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self.cpu.wb_adr,
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self.cpu.wb_we,
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self.cpu.wb_ack,
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self.cpu.wb_sel,
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self.cpu.wb_datw,
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self.cpu.wb.datr,
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]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 512,
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clock_domain = 'sys',
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csr_csv = 'analyzer.csv')
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self.add_csr('analyzer')
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description='A2O Test')
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parser.add_argument('--build', action='store_true', help='Build bitstream')
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parser.add_argument('--load', action='store_true', help='Load bitstream')
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parser.add_argument('--sys-clk-freq', default=100e6, help='System clock frequency (default: 100MHz)')
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parser.add_argument('--with-analyzer', action='store_true', help='Include analyzer')
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builder_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_analyzer = args.with_analyzer,
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if __name__ == '__main__':
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main()
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