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1093 lines
42 KiB
Plaintext
1093 lines
42 KiB
Plaintext
3 years ago
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OpenROAD v2.0-1901-g6157d4945
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This program is licensed under the BSD-3 license. See the LICENSE file for details.
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Components of this program may be licensed under more restrictive licenses which must be honored.
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[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
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[INFO ODB-0223] Created 11 technology layers
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[INFO ODB-0224] Created 25 technology vias
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[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
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[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
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[INFO ODB-0225] Created 437 library cells
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[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
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[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_cts.def
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[INFO ODB-0128] Design: A2P_WB
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[INFO ODB-0094] Created 100000 Insts
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[INFO ODB-0094] Created 200000 Insts
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[INFO ODB-0094] Created 300000 Insts
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[INFO ODB-0094] Created 400000 Insts
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[INFO ODB-0094] Created 500000 Insts
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[INFO ODB-0094] Created 600000 Insts
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[INFO ODB-0094] Created 700000 Insts
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[INFO ODB-0094] Created 800000 Insts
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[INFO ODB-0094] Created 900000 Insts
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[INFO ODB-0094] Created 1000000 Insts
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[INFO ODB-0094] Created 1100000 Insts
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[INFO ODB-0094] Created 1200000 Insts
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[INFO ODB-0094] Created 1300000 Insts
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[INFO ODB-0094] Created 1400000 Insts
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[INFO ODB-0094] Created 1500000 Insts
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[INFO ODB-0094] Created 1600000 Insts
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[INFO ODB-0094] Created 1700000 Insts
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[INFO ODB-0094] Created 1800000 Insts
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[INFO ODB-0094] Created 1900000 Insts
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[INFO ODB-0094] Created 2000000 Insts
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[INFO ODB-0094] Created 2100000 Insts
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[INFO ODB-0094] Created 2200000 Insts
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[INFO ODB-0094] Created 2300000 Insts
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[INFO ODB-0094] Created 2400000 Insts
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[INFO ODB-0094] Created 2500000 Insts
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[INFO ODB-0094] Created 2600000 Insts
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[INFO ODB-0130] Created 254 pins.
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[INFO ODB-0131] Created 2678419 components and 5653812 component-terminals.
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[INFO ODB-0132] Created 2 special nets and 5356838 connections.
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[INFO ODB-0133] Created 83035 nets and 296646 connections.
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[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_cts.def
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[INFO ORD-0030] Using 6 thread(s).
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[INFO DRT-0149] Reading tech and libs.
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Units: 1000
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Number of layers: 13
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Number of macros: 437
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Number of vias: 25
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Number of viarulegen: 25
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[INFO DRT-0150] Reading design.
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Design: A2P_WB
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Die area: ( 0 0 ) ( 5200000 4609140 )
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Number of track patterns: 12
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Number of DEF vias: 4
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Number of components: 2678419
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Number of terminals: 254
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Number of snets: 2
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Number of nets: 83035
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[INFO DRT-0151] Reading guide.
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[INFO DRT-0156] guideIn read 100000 guides.
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[INFO DRT-0156] guideIn read 200000 guides.
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[INFO DRT-0156] guideIn read 300000 guides.
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[INFO DRT-0156] guideIn read 400000 guides.
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[INFO DRT-0156] guideIn read 500000 guides.
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[INFO DRT-0156] guideIn read 600000 guides.
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[INFO DRT-0156] guideIn read 700000 guides.
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Number of guides: 708948
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[INFO DRT-0167] List of default vias:
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Layer mcon
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default via: L1M1_PR
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Layer via
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default via: M1M2_PR
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Layer via2
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default via: M2M3_PR
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Layer via3
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default via: M3M4_PR
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Layer via4
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default via: M4M5_PR_MR
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[INFO DRT-0162] Library cell analysis.
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[INFO DRT-0163] Instance analysis.
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Complete 10000 instances.
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Complete 20000 instances.
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Complete 30000 instances.
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Complete 40000 instances.
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Complete 50000 instances.
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Complete 60000 instances.
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Complete 70000 instances.
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Complete 80000 instances.
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Complete 90000 instances.
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Complete 100000 instances.
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Complete 200000 instances.
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Complete 300000 instances.
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Complete 400000 instances.
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Complete 500000 instances.
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Complete 600000 instances.
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Complete 700000 instances.
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Complete 800000 instances.
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Complete 900000 instances.
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Complete 1000000 instances.
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Complete 1100000 instances.
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Complete 1200000 instances.
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Complete 1300000 instances.
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Complete 1400000 instances.
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Complete 1500000 instances.
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Complete 1600000 instances.
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Complete 1700000 instances.
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Complete 1800000 instances.
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Complete 1900000 instances.
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Complete 2000000 instances.
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Complete 2100000 instances.
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Complete 2200000 instances.
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Complete 2300000 instances.
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Complete 2400000 instances.
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Complete 2500000 instances.
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Complete 2600000 instances.
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[INFO DRT-0164] Number of unique instances = 402.
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[INFO DRT-0168] Init region query.
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[INFO DRT-0018] Complete 10000 insts.
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[INFO DRT-0018] Complete 20000 insts.
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[INFO DRT-0018] Complete 30000 insts.
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[INFO DRT-0018] Complete 40000 insts.
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[INFO DRT-0018] Complete 50000 insts.
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[INFO DRT-0018] Complete 60000 insts.
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[INFO DRT-0018] Complete 70000 insts.
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[INFO DRT-0018] Complete 80000 insts.
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[INFO DRT-0018] Complete 90000 insts.
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[INFO DRT-0019] Complete 100000 insts.
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[INFO DRT-0019] Complete 200000 insts.
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[INFO DRT-0019] Complete 300000 insts.
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[INFO DRT-0019] Complete 400000 insts.
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[INFO DRT-0019] Complete 500000 insts.
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[INFO DRT-0019] Complete 600000 insts.
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[INFO DRT-0019] Complete 700000 insts.
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[INFO DRT-0019] Complete 800000 insts.
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[INFO DRT-0019] Complete 900000 insts.
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[INFO DRT-0019] Complete 1000000 insts.
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[INFO DRT-0019] Complete 1100000 insts.
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[INFO DRT-0019] Complete 1200000 insts.
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[INFO DRT-0019] Complete 1300000 insts.
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[INFO DRT-0019] Complete 1400000 insts.
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[INFO DRT-0019] Complete 1500000 insts.
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[INFO DRT-0019] Complete 1600000 insts.
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[INFO DRT-0019] Complete 1700000 insts.
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|
[INFO DRT-0019] Complete 1800000 insts.
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[INFO DRT-0019] Complete 1900000 insts.
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[INFO DRT-0019] Complete 2000000 insts.
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[INFO DRT-0019] Complete 2100000 insts.
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[INFO DRT-0019] Complete 2200000 insts.
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[INFO DRT-0019] Complete 2300000 insts.
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[INFO DRT-0019] Complete 2400000 insts.
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[INFO DRT-0019] Complete 2500000 insts.
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[INFO DRT-0019] Complete 2600000 insts.
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[INFO DRT-0024] Complete FR_MASTERSLICE.
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[INFO DRT-0024] Complete FR_VIA.
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[INFO DRT-0024] Complete li1.
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[INFO DRT-0024] Complete mcon.
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[INFO DRT-0024] Complete met1.
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[INFO DRT-0024] Complete via.
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[INFO DRT-0024] Complete met2.
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[INFO DRT-0024] Complete via2.
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[INFO DRT-0024] Complete met3.
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[INFO DRT-0024] Complete via3.
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[INFO DRT-0024] Complete met4.
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[INFO DRT-0024] Complete via4.
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[INFO DRT-0024] Complete met5.
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[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
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[INFO DRT-0033] FR_VIA shape region query size = 0.
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[INFO DRT-0033] li1 shape region query size = 8868617.
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[INFO DRT-0033] mcon shape region query size = 166205.
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[INFO DRT-0033] met1 shape region query size = 6021926.
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[INFO DRT-0033] via shape region query size = 1351680.
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[INFO DRT-0033] met2 shape region query size = 540889.
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[INFO DRT-0033] via2 shape region query size = 1081344.
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[INFO DRT-0033] met3 shape region query size = 540709.
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[INFO DRT-0033] via3 shape region query size = 1081344.
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[INFO DRT-0033] met4 shape region query size = 324544.
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[INFO DRT-0033] via4 shape region query size = 53856.
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[INFO DRT-0033] met5 shape region query size = 54162.
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[INFO DRT-0165] Start pin access.
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[INFO DRT-0076] Complete 100 pins.
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[INFO DRT-0076] Complete 200 pins.
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[INFO DRT-0076] Complete 300 pins.
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[INFO DRT-0076] Complete 400 pins.
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[INFO DRT-0076] Complete 500 pins.
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[INFO DRT-0076] Complete 600 pins.
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[INFO DRT-0076] Complete 700 pins.
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[INFO DRT-0076] Complete 800 pins.
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[INFO DRT-0076] Complete 900 pins.
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[INFO DRT-0077] Complete 1000 pins.
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[INFO DRT-0078] Complete 1758 pins.
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[INFO DRT-0079] Complete 100 unique inst patterns.
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[INFO DRT-0079] Complete 200 unique inst patterns.
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[INFO DRT-0079] Complete 300 unique inst patterns.
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[INFO DRT-0081] Complete 392 unique inst patterns.
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[INFO DRT-0082] Complete 1000 groups.
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[INFO DRT-0082] Complete 2000 groups.
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[INFO DRT-0082] Complete 3000 groups.
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[INFO DRT-0082] Complete 4000 groups.
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[INFO DRT-0082] Complete 5000 groups.
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[INFO DRT-0082] Complete 6000 groups.
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[INFO DRT-0082] Complete 7000 groups.
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[INFO DRT-0082] Complete 8000 groups.
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[INFO DRT-0082] Complete 9000 groups.
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[INFO DRT-0083] Complete 10000 groups.
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[INFO DRT-0083] Complete 20000 groups.
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[INFO DRT-0083] Complete 30000 groups.
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[INFO DRT-0083] Complete 40000 groups.
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[INFO DRT-0083] Complete 50000 groups.
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[INFO DRT-0083] Complete 60000 groups.
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[INFO DRT-0083] Complete 70000 groups.
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[INFO DRT-0083] Complete 80000 groups.
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[INFO DRT-0084] Complete 83820 groups.
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#scanned instances = 2678419
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#unique instances = 402
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#stdCellGenAp = 13712
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#stdCellValidPlanarAp = 208
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#stdCellValidViaAp = 10333
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#stdCellPinNoAp = 0
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#stdCellPinCnt = 296646
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#instTermValidViaApCnt = 0
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#macroGenAp = 0
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#macroValidPlanarAp = 0
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#macroValidViaAp = 0
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#macroNoAp = 0
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[INFO DRT-0166] Complete pin access.
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[INFO DRT-0267] cpu time = 00:00:11, elapsed time = 00:00:03, memory = 4445.77 (MB), peak = 4445.77 (MB)
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[INFO DRT-0169] Post process guides.
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[INFO DRT-0176] GCELLGRID X 0 DO 667 STEP 6900 ;
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[INFO DRT-0177] GCELLGRID Y 0 DO 753 STEP 6900 ;
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[INFO DRT-0026] Complete 10000 origin guides.
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[INFO DRT-0026] Complete 20000 origin guides.
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[INFO DRT-0026] Complete 30000 origin guides.
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[INFO DRT-0026] Complete 40000 origin guides.
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[INFO DRT-0026] Complete 50000 origin guides.
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[INFO DRT-0026] Complete 60000 origin guides.
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[INFO DRT-0026] Complete 70000 origin guides.
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[INFO DRT-0026] Complete 80000 origin guides.
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[INFO DRT-0026] Complete 90000 origin guides.
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|
[INFO DRT-0027] Complete 100000 origin guides.
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[INFO DRT-0027] Complete 200000 origin guides.
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[INFO DRT-0027] Complete 300000 origin guides.
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||
|
[INFO DRT-0027] Complete 400000 origin guides.
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||
|
[INFO DRT-0027] Complete 500000 origin guides.
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[INFO DRT-0027] Complete 600000 origin guides.
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[INFO DRT-0027] Complete 700000 origin guides.
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[INFO DRT-0028] Complete FR_MASTERSLICE.
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[INFO DRT-0028] Complete FR_VIA.
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[INFO DRT-0028] Complete li1.
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[INFO DRT-0028] Complete mcon.
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[INFO DRT-0028] Complete met1.
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[INFO DRT-0028] Complete via.
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[INFO DRT-0028] Complete met2.
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[INFO DRT-0028] Complete via2.
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[INFO DRT-0028] Complete met3.
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[INFO DRT-0028] Complete via3.
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[INFO DRT-0028] Complete met4.
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[INFO DRT-0028] Complete via4.
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[INFO DRT-0028] Complete met5.
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complete 10000 nets.
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complete 20000 nets.
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complete 30000 nets.
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complete 40000 nets.
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complete 50000 nets.
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complete 60000 nets.
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complete 70000 nets.
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complete 80000 nets.
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|
[INFO DRT-0178] Init guide query.
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|
[INFO DRT-0029] Complete 10000 nets (guide).
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[INFO DRT-0029] Complete 20000 nets (guide).
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[INFO DRT-0029] Complete 30000 nets (guide).
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|
[INFO DRT-0029] Complete 40000 nets (guide).
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||
|
[INFO DRT-0029] Complete 50000 nets (guide).
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|
[INFO DRT-0029] Complete 60000 nets (guide).
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|
[INFO DRT-0029] Complete 70000 nets (guide).
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|
[INFO DRT-0029] Complete 80000 nets (guide).
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|
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
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|
[INFO DRT-0035] Complete FR_VIA (guide).
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|
[INFO DRT-0035] Complete li1 (guide).
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|
[INFO DRT-0035] Complete mcon (guide).
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|
[INFO DRT-0035] Complete met1 (guide).
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|
[INFO DRT-0035] Complete via (guide).
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|
[INFO DRT-0035] Complete met2 (guide).
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|
[INFO DRT-0035] Complete via2 (guide).
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|
[INFO DRT-0035] Complete met3 (guide).
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|
[INFO DRT-0035] Complete via3 (guide).
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||
|
[INFO DRT-0035] Complete met4 (guide).
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|
[INFO DRT-0035] Complete via4 (guide).
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|
[INFO DRT-0035] Complete met5 (guide).
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|
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
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|
[INFO DRT-0036] FR_VIA guide region query size = 0.
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|
[INFO DRT-0036] li1 guide region query size = 253790.
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|
[INFO DRT-0036] mcon guide region query size = 0.
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|
[INFO DRT-0036] met1 guide region query size = 215326.
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[INFO DRT-0036] via guide region query size = 0.
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|
[INFO DRT-0036] met2 guide region query size = 126545.
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|
[INFO DRT-0036] via2 guide region query size = 0.
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[INFO DRT-0036] met3 guide region query size = 6001.
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|
[INFO DRT-0036] via3 guide region query size = 0.
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|
[INFO DRT-0036] met4 guide region query size = 1532.
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|
[INFO DRT-0036] via4 guide region query size = 0.
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[INFO DRT-0036] met5 guide region query size = 2.
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|
[INFO DRT-0179] Init gr pin query.
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[INFO DRT-0185] Post process initialize RPin region query.
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|
[INFO DRT-0181] Start track assignment.
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[INFO DRT-0184] Done with 381867 vertical wires in 16 frboxes and 221329 horizontal wires in 14 frboxes.
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[INFO DRT-0186] Done with 65662 vertical wires in 16 frboxes and 59551 horizontal wires in 14 frboxes.
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[INFO DRT-0182] Complete track assignment.
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|
[INFO DRT-0267] cpu time = 00:02:53, elapsed time = 00:00:50, memory = 6351.11 (MB), peak = 6825.89 (MB)
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|
[INFO DRT-0187] Start routing data preparation.
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[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6351.11 (MB), peak = 6825.89 (MB)
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[INFO DRT-0194] Start detail routing.
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|
[INFO DRT-0195] Start 0th optimization iteration.
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|
Completing 10% with 1596 violations.
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elapsed time = 00:00:15, memory = 6540.95 (MB).
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|
Completing 20% with 8031 violations.
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||
|
elapsed time = 00:00:58, memory = 8531.58 (MB).
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|
Completing 30% with 8033 violations.
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||
|
elapsed time = 00:01:01, memory = 8531.58 (MB).
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|
Completing 40% with 9404 violations.
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||
|
elapsed time = 00:01:45, memory = 8492.78 (MB).
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|
Completing 50% with 14833 violations.
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||
|
elapsed time = 00:02:03, memory = 8696.30 (MB).
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||
|
Completing 60% with 16256 violations.
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||
|
elapsed time = 00:02:23, memory = 8630.54 (MB).
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||
|
Completing 70% with 21841 violations.
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||
|
elapsed time = 00:03:17, memory = 8785.66 (MB).
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||
|
Completing 80% with 21840 violations.
|
||
|
elapsed time = 00:03:19, memory = 8785.66 (MB).
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||
|
Completing 90% with 22953 violations.
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||
|
elapsed time = 00:04:15, memory = 8768.04 (MB).
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||
|
Completing 100% with 27811 violations.
|
||
|
elapsed time = 00:04:33, memory = 8934.45 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 79014.
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||
|
[INFO DRT-0267] cpu time = 00:26:17, elapsed time = 00:04:36, memory = 8904.70 (MB), peak = 8942.63 (MB)
|
||
|
Total wire length = 4865863 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2051450 um.
|
||
|
Total wire length on LAYER met2 = 2051717 um.
|
||
|
Total wire length on LAYER met3 = 535490 um.
|
||
|
Total wire length on LAYER met4 = 226839 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 681135.
|
||
|
Up-via summary (total 681135):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296181
|
||
|
met1 372089
|
||
|
met2 10015
|
||
|
met3 2846
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
681135
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 1st optimization iteration.
|
||
|
Completing 10% with 75512 violations.
|
||
|
elapsed time = 00:00:11, memory = 8904.70 (MB).
|
||
|
Completing 20% with 60710 violations.
|
||
|
elapsed time = 00:00:45, memory = 8990.31 (MB).
|
||
|
Completing 30% with 60709 violations.
|
||
|
elapsed time = 00:00:48, memory = 8990.31 (MB).
|
||
|
Completing 40% with 57397 violations.
|
||
|
elapsed time = 00:01:20, memory = 8990.31 (MB).
|
||
|
Completing 50% with 43446 violations.
|
||
|
elapsed time = 00:01:35, memory = 9012.08 (MB).
|
||
|
Completing 60% with 39413 violations.
|
||
|
elapsed time = 00:01:49, memory = 9012.08 (MB).
|
||
|
Completing 70% with 24476 violations.
|
||
|
elapsed time = 00:02:26, memory = 9028.84 (MB).
|
||
|
Completing 80% with 24475 violations.
|
||
|
elapsed time = 00:02:28, memory = 9028.84 (MB).
|
||
|
Completing 90% with 20772 violations.
|
||
|
elapsed time = 00:03:04, memory = 9028.84 (MB).
|
||
|
Completing 100% with 6614 violations.
|
||
|
elapsed time = 00:03:18, memory = 8987.64 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 6621.
|
||
|
[INFO DRT-0267] cpu time = 00:18:38, elapsed time = 00:03:21, memory = 8987.64 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4827617 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2035397 um.
|
||
|
Total wire length on LAYER met2 = 2031566 um.
|
||
|
Total wire length on LAYER met3 = 534026 um.
|
||
|
Total wire length on LAYER met4 = 226260 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676745.
|
||
|
Up-via summary (total 676745):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296144
|
||
|
met1 367687
|
||
|
met2 10107
|
||
|
met3 2803
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676745
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 2nd optimization iteration.
|
||
|
Completing 10% with 6542 violations.
|
||
|
elapsed time = 00:00:06, memory = 8972.93 (MB).
|
||
|
Completing 20% with 6179 violations.
|
||
|
elapsed time = 00:00:36, memory = 8973.04 (MB).
|
||
|
Completing 30% with 6179 violations.
|
||
|
elapsed time = 00:00:36, memory = 8973.04 (MB).
|
||
|
Completing 40% with 6050 violations.
|
||
|
elapsed time = 00:01:01, memory = 8973.04 (MB).
|
||
|
Completing 50% with 5789 violations.
|
||
|
elapsed time = 00:01:17, memory = 8973.04 (MB).
|
||
|
Completing 60% with 5789 violations.
|
||
|
elapsed time = 00:01:23, memory = 8973.04 (MB).
|
||
|
Completing 70% with 5592 violations.
|
||
|
elapsed time = 00:01:53, memory = 8973.04 (MB).
|
||
|
Completing 80% with 5251 violations.
|
||
|
elapsed time = 00:01:56, memory = 8973.04 (MB).
|
||
|
Completing 90% with 5191 violations.
|
||
|
elapsed time = 00:02:22, memory = 8973.04 (MB).
|
||
|
Completing 100% with 4695 violations.
|
||
|
elapsed time = 00:02:32, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 4701.
|
||
|
[INFO DRT-0267] cpu time = 00:14:10, elapsed time = 00:02:35, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4811613 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2027887 um.
|
||
|
Total wire length on LAYER met2 = 2022697 um.
|
||
|
Total wire length on LAYER met3 = 534164 um.
|
||
|
Total wire length on LAYER met4 = 226498 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 674207.
|
||
|
Up-via summary (total 674207):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 365256
|
||
|
met2 9977
|
||
|
met3 2825
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
674207
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 3rd optimization iteration.
|
||
|
Completing 10% with 4524 violations.
|
||
|
elapsed time = 00:00:04, memory = 8973.04 (MB).
|
||
|
Completing 20% with 3546 violations.
|
||
|
elapsed time = 00:00:17, memory = 8973.04 (MB).
|
||
|
Completing 30% with 3546 violations.
|
||
|
elapsed time = 00:00:17, memory = 8973.04 (MB).
|
||
|
Completing 40% with 3364 violations.
|
||
|
elapsed time = 00:00:27, memory = 8973.04 (MB).
|
||
|
Completing 50% with 2386 violations.
|
||
|
elapsed time = 00:00:34, memory = 8973.04 (MB).
|
||
|
Completing 60% with 2217 violations.
|
||
|
elapsed time = 00:00:37, memory = 8973.04 (MB).
|
||
|
Completing 70% with 1265 violations.
|
||
|
elapsed time = 00:00:51, memory = 8973.04 (MB).
|
||
|
Completing 80% with 1265 violations.
|
||
|
elapsed time = 00:00:51, memory = 8973.04 (MB).
|
||
|
Completing 90% with 1088 violations.
|
||
|
elapsed time = 00:01:04, memory = 8973.04 (MB).
|
||
|
Completing 100% with 196 violations.
|
||
|
elapsed time = 00:01:09, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 196.
|
||
|
[INFO DRT-0267] cpu time = 00:05:39, elapsed time = 00:01:10, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810332 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2015138 um.
|
||
|
Total wire length on LAYER met2 = 2023765 um.
|
||
|
Total wire length on LAYER met3 = 544366 um.
|
||
|
Total wire length on LAYER met4 = 226696 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676774.
|
||
|
Up-via summary (total 676774):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366392
|
||
|
met2 11392
|
||
|
met3 2841
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676774
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 4th optimization iteration.
|
||
|
Completing 10% with 195 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 20% with 150 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 30% with 150 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 40% with 139 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 50% with 87 violations.
|
||
|
elapsed time = 00:00:03, memory = 8973.04 (MB).
|
||
|
Completing 60% with 81 violations.
|
||
|
elapsed time = 00:00:03, memory = 8973.04 (MB).
|
||
|
Completing 70% with 48 violations.
|
||
|
elapsed time = 00:00:05, memory = 8973.04 (MB).
|
||
|
Completing 80% with 48 violations.
|
||
|
elapsed time = 00:00:05, memory = 8973.04 (MB).
|
||
|
Completing 90% with 44 violations.
|
||
|
elapsed time = 00:00:05, memory = 8973.04 (MB).
|
||
|
Completing 100% with 9 violations.
|
||
|
elapsed time = 00:00:07, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 9.
|
||
|
[INFO DRT-0267] cpu time = 00:00:21, elapsed time = 00:00:07, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810215 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014688 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544671 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676852.
|
||
|
Up-via summary (total 676852):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366418
|
||
|
met2 11442
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676852
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 5th optimization iteration.
|
||
|
Completing 10% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 9 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 8 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 80% with 8 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 90% with 8 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 100% with 8 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 8.
|
||
|
[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:01, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810216 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014688 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544671 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676852.
|
||
|
Up-via summary (total 676852):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366418
|
||
|
met2 11442
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676852
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 6th optimization iteration.
|
||
|
Completing 10% with 8 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 3 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 80% with 3 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 90% with 3 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 100% with 3 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 3.
|
||
|
[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:02, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810215 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014683 um.
|
||
|
Total wire length on LAYER met2 = 2023776 um.
|
||
|
Total wire length on LAYER met3 = 544672 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676854.
|
||
|
Up-via summary (total 676854):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11443
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676854
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 7th optimization iteration.
|
||
|
Completing 10% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 3 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 2 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 90% with 2 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
Completing 100% with 2 violations.
|
||
|
elapsed time = 00:00:02, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 2.
|
||
|
[INFO DRT-0267] cpu time = 00:00:04, elapsed time = 00:00:02, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810218 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014680 um.
|
||
|
Total wire length on LAYER met2 = 2023782 um.
|
||
|
Total wire length on LAYER met3 = 544671 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676854.
|
||
|
Up-via summary (total 676854):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11443
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676854
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 8th optimization iteration.
|
||
|
Completing 10% with 2 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 30% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 40% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 50% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 60% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 70% with 2 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 80% with 1 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 90% with 1 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
Completing 100% with 1 violations.
|
||
|
elapsed time = 00:00:01, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 1.
|
||
|
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810218 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014681 um.
|
||
|
Total wire length on LAYER met2 = 2023781 um.
|
||
|
Total wire length on LAYER met3 = 544671 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676855.
|
||
|
Up-via summary (total 676855):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366420
|
||
|
met2 11443
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676855
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 9th optimization iteration.
|
||
|
Completing 10% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 1.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810218 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014681 um.
|
||
|
Total wire length on LAYER met2 = 2023781 um.
|
||
|
Total wire length on LAYER met3 = 544671 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676855.
|
||
|
Up-via summary (total 676855):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366420
|
||
|
met2 11443
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676855
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 10th optimization iteration.
|
||
|
Completing 10% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 1 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 17th optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 25th optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 33rd optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 41st optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 49th optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0195] Start 57th optimization iteration.
|
||
|
Completing 10% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 20% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 30% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 40% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 50% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 60% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 70% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 80% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 90% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
Completing 100% with 0 violations.
|
||
|
elapsed time = 00:00:00, memory = 8973.04 (MB).
|
||
|
[INFO DRT-0199] Number of violations = 0.
|
||
|
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0198] Complete detail routing.
|
||
|
Total wire length = 4810208 um.
|
||
|
Total wire length on LAYER li1 = 0 um.
|
||
|
Total wire length on LAYER met1 = 2014661 um.
|
||
|
Total wire length on LAYER met2 = 2023773 um.
|
||
|
Total wire length on LAYER met3 = 544690 um.
|
||
|
Total wire length on LAYER met4 = 226718 um.
|
||
|
Total wire length on LAYER met5 = 365 um.
|
||
|
Total number of vias = 676856.
|
||
|
Up-via summary (total 676856):.
|
||
|
|
||
|
-------------------------
|
||
|
FR_MASTERSLICE 0
|
||
|
li1 296145
|
||
|
met1 366419
|
||
|
met2 11445
|
||
|
met3 2843
|
||
|
met4 4
|
||
|
-------------------------
|
||
|
676856
|
||
|
|
||
|
|
||
|
[INFO DRT-0267] cpu time = 01:05:23, elapsed time = 00:12:04, memory = 8973.04 (MB), peak = 9046.82 (MB)
|
||
|
|
||
|
[INFO DRT-0180] Post processing.
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Elapsed time: 13:33.88[h:]min:sec. CPU time: user 4136.68 sys 5.21 (508%). Peak memory: 9263940KB.
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