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69 lines
1.3 KiB
Markdown
69 lines
1.3 KiB
Markdown
2 years ago
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# A2 Interfaces to WB
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* core interfaces
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* A2I/A2O A2L2 bus
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* Single (combined I/D) w/SMP extensions
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* Dual (separate I/D) WB buses w/SMP extensions
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* bus interfaces
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* single WB
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* dual WB
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* functions
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* queues one or more core commands
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* point of coherncy for larx/stcx, sync, tlbie, etc. for multicores below it (single/mulithread)
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* address compares necessary for ordering/coherency
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* optional mailbox interface for core-core peer and broadcast
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* arbitrates for WB bus(es)
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* gen responses for cores
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## Possible configurations
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* one core, WB: pass-through with SMP functions
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* one core, A2L2: bridge with SMP functions
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* multi-core: identical or mixed WB1/WB2/A2L2, queueing, arbitration, and SMP functions
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### syntax check
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```verilator --lint-only a2wb.v -Wno-LITENDIAN```
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### sim build
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```
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verilator --cc --exe --trace -Wno-Litendian -Wno-fatal -I./src top.v tb.cpp
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cd obj_dir;make -f Vtop.mk;cd ..
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obj_dir/Vtop
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```
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### synth build (Litex)
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* had to make some source changes for Vivado
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```
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rm obj_dir/*
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# use sim top so tb.cpp is ok
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verilator --cc --exe --trace -Wno-Litendian -Wno-fatal -I./litex/a2node/verilog -I./src top.v tb.cpp uart.cpp
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cd obj_dir;make -f Vtop.mk;cd ..
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obj_dir/Vtop
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gtkwave wtf.vcd wtf.gtkw
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vcd2fst wtf.vcd wtf.fst
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gtkwave wtf.fst wtf.gtkw
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```
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