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a2p/build/litex/litex-1099/master/cmod7.v

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add uart test
3 years ago
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : cmod7.v
// Device : xc7a35t-CPG236-1
// LiteX sha1 : feca1c47
// Date : 2021-11-11 08:18:47
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------
module cmod7 (
output reg serial_tx,
input wire serial_rx,
(* dont_touch = "true" *) input wire clk12,
output wire [18:0] issiram_addr,
inout wire [7:0] issiram_data,
output wire issiram_oen,
output wire issiram_wen,
output wire issiram_cen,
output reg user_led0,
output reg user_led1,
input wire user_btn0,
input wire user_btn1,
inout wire pmod0,
inout wire pmod1,
output reg digital10,
input wire digital11,
output wire digital43
);
//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------
reg basesoc_soc_rst = 1'd0;
wire basesoc_cpu_rst;
reg [1:0] basesoc_reset_storage = 2'd0;
reg basesoc_reset_re = 1'd0;
reg [31:0] basesoc_scratch_storage = 32'd305419896;
reg basesoc_scratch_re = 1'd0;
wire [31:0] basesoc_bus_errors_status;
wire basesoc_bus_errors_we;
reg basesoc_bus_errors_re = 1'd0;
wire basesoc_bus_error;
reg [31:0] basesoc_bus_errors = 32'd0;
wire basesoc_reset;
reg [31:0] basesoc_interrupt = 32'd0;
reg basesoc_interruptS = 1'd0;
wire [29:0] basesoc_ibus_adr;
wire [31:0] basesoc_ibus_dat_w;
wire [31:0] basesoc_ibus_dat_r;
wire [3:0] basesoc_ibus_sel;
wire basesoc_ibus_cyc;
wire basesoc_ibus_stb;
wire basesoc_ibus_ack;
wire basesoc_ibus_we;
wire [2:0] basesoc_ibus_cti;
wire [1:0] basesoc_ibus_bte;
wire basesoc_ibus_err;
wire [29:0] basesoc_dbus_adr;
wire [31:0] basesoc_dbus_dat_w;
wire [31:0] basesoc_dbus_dat_r;
wire [3:0] basesoc_dbus_sel;
wire basesoc_dbus_cyc;
wire basesoc_dbus_stb;
wire basesoc_dbus_ack;
wire basesoc_dbus_we;
wire [2:0] basesoc_dbus_cti;
wire [1:0] basesoc_dbus_bte;
wire basesoc_dbus_err;
reg [31:0] basesoc_a2p = 32'd0;
wire basesoc_tx_sink_valid;
reg basesoc_tx_sink_ready = 1'd0;
wire basesoc_tx_sink_first;
wire basesoc_tx_sink_last;
wire [7:0] basesoc_tx_sink_payload_data;
reg [7:0] basesoc_tx_data = 8'd0;
reg [3:0] basesoc_tx_count = 4'd0;
reg basesoc_tx_enable = 1'd0;
reg basesoc_tx_tick = 1'd0;
reg [31:0] basesoc_tx_phase = 32'd0;
reg basesoc_rx_source_valid = 1'd0;
wire basesoc_rx_source_ready;
reg basesoc_rx_source_first = 1'd0;
reg basesoc_rx_source_last = 1'd0;
reg [7:0] basesoc_rx_source_payload_data = 8'd0;
reg [7:0] basesoc_rx_data = 8'd0;
reg [3:0] basesoc_rx_count = 4'd0;
reg basesoc_rx_enable = 1'd0;
reg basesoc_rx_tick = 1'd0;
reg [31:0] basesoc_rx_phase = 32'd0;
wire basesoc_rx_rx;
reg basesoc_rx_rx_d = 1'd0;
reg basesoc_uart_rxtx_re = 1'd0;
wire [7:0] basesoc_uart_rxtx_r;
reg basesoc_uart_rxtx_we = 1'd0;
wire [7:0] basesoc_uart_rxtx_w;
wire basesoc_uart_txfull_status;
wire basesoc_uart_txfull_we;
reg basesoc_uart_txfull_re = 1'd0;
wire basesoc_uart_rxempty_status;
wire basesoc_uart_rxempty_we;
reg basesoc_uart_rxempty_re = 1'd0;
wire basesoc_uart_irq;
wire basesoc_uart_tx_status;
reg basesoc_uart_tx_pending = 1'd0;
wire basesoc_uart_tx_trigger;
reg basesoc_uart_tx_clear = 1'd0;
reg basesoc_uart_tx_trigger_d = 1'd0;
wire basesoc_uart_rx_status;
reg basesoc_uart_rx_pending = 1'd0;
wire basesoc_uart_rx_trigger;
reg basesoc_uart_rx_clear = 1'd0;
reg basesoc_uart_rx_trigger_d = 1'd0;
wire basesoc_uart_tx0;
wire basesoc_uart_rx0;
reg [1:0] basesoc_uart_status_status = 2'd0;
wire basesoc_uart_status_we;
reg basesoc_uart_status_re = 1'd0;
wire basesoc_uart_tx1;
wire basesoc_uart_rx1;
reg [1:0] basesoc_uart_pending_status = 2'd0;
wire basesoc_uart_pending_we;
reg basesoc_uart_pending_re = 1'd0;
reg [1:0] basesoc_uart_pending_r = 2'd0;
wire basesoc_uart_tx2;
wire basesoc_uart_rx2;
reg [1:0] basesoc_uart_enable_storage = 2'd0;
reg basesoc_uart_enable_re = 1'd0;
wire basesoc_uart_txempty_status;
wire basesoc_uart_txempty_we;
reg basesoc_uart_txempty_re = 1'd0;
wire basesoc_uart_rxfull_status;
wire basesoc_uart_rxfull_we;
reg basesoc_uart_rxfull_re = 1'd0;
wire basesoc_uart_uart_sink_valid;
wire basesoc_uart_uart_sink_ready;
wire basesoc_uart_uart_sink_first;
wire basesoc_uart_uart_sink_last;
wire [7:0] basesoc_uart_uart_sink_payload_data;
wire basesoc_uart_uart_source_valid;
wire basesoc_uart_uart_source_ready;
wire basesoc_uart_uart_source_first;
wire basesoc_uart_uart_source_last;
wire [7:0] basesoc_uart_uart_source_payload_data;
wire basesoc_uart_tx_fifo_sink_valid;
wire basesoc_uart_tx_fifo_sink_ready;
reg basesoc_uart_tx_fifo_sink_first = 1'd0;
reg basesoc_uart_tx_fifo_sink_last = 1'd0;
wire [7:0] basesoc_uart_tx_fifo_sink_payload_data;
wire basesoc_uart_tx_fifo_source_valid;
wire basesoc_uart_tx_fifo_source_ready;
wire basesoc_uart_tx_fifo_source_first;
wire basesoc_uart_tx_fifo_source_last;
wire [7:0] basesoc_uart_tx_fifo_source_payload_data;
wire basesoc_uart_tx_fifo_re;
reg basesoc_uart_tx_fifo_readable = 1'd0;
wire basesoc_uart_tx_fifo_syncfifo_we;
wire basesoc_uart_tx_fifo_syncfifo_writable;
wire basesoc_uart_tx_fifo_syncfifo_re;
wire basesoc_uart_tx_fifo_syncfifo_readable;
wire [9:0] basesoc_uart_tx_fifo_syncfifo_din;
wire [9:0] basesoc_uart_tx_fifo_syncfifo_dout;
reg [4:0] basesoc_uart_tx_fifo_level0 = 5'd0;
reg basesoc_uart_tx_fifo_replace = 1'd0;
reg [3:0] basesoc_uart_tx_fifo_produce = 4'd0;
reg [3:0] basesoc_uart_tx_fifo_consume = 4'd0;
reg [3:0] basesoc_uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] basesoc_uart_tx_fifo_wrport_dat_r;
wire basesoc_uart_tx_fifo_wrport_we;
wire [9:0] basesoc_uart_tx_fifo_wrport_dat_w;
wire basesoc_uart_tx_fifo_do_read;
wire [3:0] basesoc_uart_tx_fifo_rdport_adr;
wire [9:0] basesoc_uart_tx_fifo_rdport_dat_r;
wire basesoc_uart_tx_fifo_rdport_re;
wire [4:0] basesoc_uart_tx_fifo_level1;
wire [7:0] basesoc_uart_tx_fifo_fifo_in_payload_data;
wire basesoc_uart_tx_fifo_fifo_in_first;
wire basesoc_uart_tx_fifo_fifo_in_last;
wire [7:0] basesoc_uart_tx_fifo_fifo_out_payload_data;
wire basesoc_uart_tx_fifo_fifo_out_first;
wire basesoc_uart_tx_fifo_fifo_out_last;
wire basesoc_uart_rx_fifo_sink_valid;
wire basesoc_uart_rx_fifo_sink_ready;
wire basesoc_uart_rx_fifo_sink_first;
wire basesoc_uart_rx_fifo_sink_last;
wire [7:0] basesoc_uart_rx_fifo_sink_payload_data;
wire basesoc_uart_rx_fifo_source_valid;
wire basesoc_uart_rx_fifo_source_ready;
wire basesoc_uart_rx_fifo_source_first;
wire basesoc_uart_rx_fifo_source_last;
wire [7:0] basesoc_uart_rx_fifo_source_payload_data;
wire basesoc_uart_rx_fifo_re;
reg basesoc_uart_rx_fifo_readable = 1'd0;
wire basesoc_uart_rx_fifo_syncfifo_we;
wire basesoc_uart_rx_fifo_syncfifo_writable;
wire basesoc_uart_rx_fifo_syncfifo_re;
wire basesoc_uart_rx_fifo_syncfifo_readable;
wire [9:0] basesoc_uart_rx_fifo_syncfifo_din;
wire [9:0] basesoc_uart_rx_fifo_syncfifo_dout;
reg [4:0] basesoc_uart_rx_fifo_level0 = 5'd0;
reg basesoc_uart_rx_fifo_replace = 1'd0;
reg [3:0] basesoc_uart_rx_fifo_produce = 4'd0;
reg [3:0] basesoc_uart_rx_fifo_consume = 4'd0;
reg [3:0] basesoc_uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] basesoc_uart_rx_fifo_wrport_dat_r;
wire basesoc_uart_rx_fifo_wrport_we;
wire [9:0] basesoc_uart_rx_fifo_wrport_dat_w;
wire basesoc_uart_rx_fifo_do_read;
wire [3:0] basesoc_uart_rx_fifo_rdport_adr;
wire [9:0] basesoc_uart_rx_fifo_rdport_dat_r;
wire basesoc_uart_rx_fifo_rdport_re;
wire [4:0] basesoc_uart_rx_fifo_level1;
wire [7:0] basesoc_uart_rx_fifo_fifo_in_payload_data;
wire basesoc_uart_rx_fifo_fifo_in_first;
wire basesoc_uart_rx_fifo_fifo_in_last;
wire [7:0] basesoc_uart_rx_fifo_fifo_out_payload_data;
wire basesoc_uart_rx_fifo_fifo_out_first;
wire basesoc_uart_rx_fifo_fifo_out_last;
reg [31:0] basesoc_timer_load_storage = 32'd0;
reg basesoc_timer_load_re = 1'd0;
reg [31:0] basesoc_timer_reload_storage = 32'd0;
reg basesoc_timer_reload_re = 1'd0;
reg basesoc_timer_en_storage = 1'd0;
reg basesoc_timer_en_re = 1'd0;
reg basesoc_timer_update_value_storage = 1'd0;
reg basesoc_timer_update_value_re = 1'd0;
reg [31:0] basesoc_timer_value_status = 32'd0;
wire basesoc_timer_value_we;
reg basesoc_timer_value_re = 1'd0;
wire basesoc_timer_irq;
wire basesoc_timer_zero_status;
reg basesoc_timer_zero_pending = 1'd0;
wire basesoc_timer_zero_trigger;
reg basesoc_timer_zero_clear = 1'd0;
reg basesoc_timer_zero_trigger_d = 1'd0;
wire basesoc_timer_zero0;
wire basesoc_timer_status_status;
wire basesoc_timer_status_we;
reg basesoc_timer_status_re = 1'd0;
wire basesoc_timer_zero1;
wire basesoc_timer_pending_status;
wire basesoc_timer_pending_we;
reg basesoc_timer_pending_re = 1'd0;
reg basesoc_timer_pending_r = 1'd0;
wire basesoc_timer_zero2;
reg basesoc_timer_enable_storage = 1'd0;
reg basesoc_timer_enable_re = 1'd0;
reg [31:0] basesoc_timer_value = 32'd0;
wire crg_rst;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire sys2x_clk;
wire idelay_clk;
wire idelay_rst;
wire crg_reset;
reg crg_power_down = 1'd0;
wire crg_locked;
(* dont_touch = "true" *) wire crg_clkin;
wire crg_clkout0;
wire crg_clkout_buf0;
wire crg_clkout1;
wire crg_clkout_buf1;
wire crg_clkout2;
wire crg_clkout_buf2;
reg [3:0] crg_reset_counter = 4'd15;
reg crg_ic_reset = 1'd1;
reg csrstorage0_storage = 1'd140989193;
reg csrstorage0_re = 1'd0;
reg csrstorage1_storage = 1'd0;
reg csrstorage1_re = 1'd0;
reg directory0_re = 1'd0;
reg directory0_r = 1'd0;
wire directory0_w;
reg csr_08000_re = 1'd0;
reg csr_08000_r = 1'd0;
wire csr_08000_w;
wire [29:0] basesoc_ram_bus_adr;
wire [31:0] basesoc_ram_bus_dat_w;
wire [31:0] basesoc_ram_bus_dat_r;
wire [3:0] basesoc_ram_bus_sel;
wire basesoc_ram_bus_cyc;
wire basesoc_ram_bus_stb;
reg basesoc_ram_bus_ack = 1'd0;
wire basesoc_ram_bus_we;
wire [2:0] basesoc_ram_bus_cti;
wire [1:0] basesoc_ram_bus_bte;
reg basesoc_ram_bus_err = 1'd0;
wire [13:0] basesoc_adr;
wire [31:0] basesoc_dat_r;
wire [29:0] sram_bus_adr;
wire [31:0] sram_bus_dat_w;
wire [31:0] sram_bus_dat_r;
wire [3:0] sram_bus_sel;
wire sram_bus_cyc;
wire sram_bus_stb;
wire sram_bus_ack;
wire sram_bus_we;
wire [2:0] sram_bus_cti;
wire [1:0] sram_bus_bte;
reg sram_bus_err = 1'd0;
reg [56:0] dna_status = 57'd0;
wire dna_we;
reg dna_re = 1'd0;
wire dna_do;
reg [6:0] dna_count = 7'd0;
wire dna_clk;
reg [11:0] xadc_temperature_status = 12'd0;
wire xadc_temperature_we;
reg xadc_temperature_re = 1'd0;
reg [11:0] xadc_vccint_status = 12'd0;
wire xadc_vccint_we;
reg xadc_vccint_re = 1'd0;
reg [11:0] xadc_vccaux_status = 12'd0;
wire xadc_vccaux_we;
reg xadc_vccaux_re = 1'd0;
reg [11:0] xadc_vccbram_status = 12'd0;
wire xadc_vccbram_we;
reg xadc_vccbram_re = 1'd0;
reg xadc_eoc_status = 1'd0;
wire xadc_eoc_we;
reg xadc_eoc_re = 1'd0;
reg xadc_eos_status = 1'd0;
wire xadc_eos_we;
reg xadc_eos_re = 1'd0;
wire [7:0] xadc_alarm;
wire xadc_ot;
wire xadc_busy;
wire [6:0] xadc_channel;
wire xadc_eoc;
wire xadc_eos;
reg xadc_dwe = 1'd0;
reg xadc_den = 1'd0;
wire xadc_drdy;
reg [6:0] xadc_dadr = 7'd0;
reg [15:0] xadc_di = 16'd0;
wire [15:0] xadc_do;
reg xadc_drp_en = 1'd0;
reg [1:0] leds_storage = 2'd0;
reg leds_re = 1'd0;
reg [1:0] leds_chaser = 2'd0;
reg leds_mode = 1'd0;
wire leds_wait;
wire leds_done;
reg [24:0] leds_count = 25'd25000000;
wire [1:0] buttons_status;
wire buttons_we;
reg buttons_re = 1'd0;
wire scl;
wire oe;
wire sda0;
reg [2:0] _w_storage = 3'd0;
reg _w_re = 1'd0;
wire sda1;
wire _r_status;
wire _r_we;
reg _r_re = 1'd0;
reg uart_1_phy_tx_sink_valid = 1'd0;
reg uart_1_phy_tx_sink_ready = 1'd0;
wire uart_1_phy_tx_sink_last;
reg [7:0] uart_1_phy_tx_sink_payload_data = 8'd0;
reg [7:0] uart_1_phy_tx_data = 8'd0;
reg [3:0] uart_1_phy_tx_count = 4'd0;
reg uart_1_phy_tx_enable = 1'd0;
reg uart_1_phy_tx_tick = 1'd0;
reg [31:0] uart_1_phy_tx_phase = 32'd0;
reg uart_1_phy_rx_source_valid = 1'd0;
reg uart_1_phy_rx_source_ready = 1'd0;
reg [7:0] uart_1_phy_rx_source_payload_data = 8'd0;
reg [7:0] uart_1_phy_rx_data = 8'd0;
reg [3:0] uart_1_phy_rx_count = 4'd0;
reg uart_1_phy_rx_enable = 1'd0;
reg uart_1_phy_rx_tick = 1'd0;
reg [31:0] uart_1_phy_rx_phase = 32'd0;
wire uart_1_phy_rx_rx;
reg uart_1_phy_rx_rx_d = 1'd0;
wire [29:0] uart_1_wishbone_adr;
wire [31:0] uart_1_wishbone_dat_w;
wire [31:0] uart_1_wishbone_dat_r;
wire [3:0] uart_1_wishbone_sel;
reg uart_1_wishbone_cyc = 1'd0;
reg uart_1_wishbone_stb = 1'd0;
wire uart_1_wishbone_ack;
reg uart_1_wishbone_we = 1'd0;
reg [2:0] uart_1_wishbone_cti = 3'd0;
reg [1:0] uart_1_wishbone_bte = 2'd0;
wire uart_1_wishbone_err;
reg [7:0] uart_1_cmd = 8'd0;
reg uart_1_incr = 1'd0;
reg [7:0] uart_1_length = 8'd0;
reg [31:0] uart_1_address = 32'd0;
reg [31:0] uart_1_data = 32'd0;
reg [1:0] uart_1_bytes_count = 2'd0;
reg [7:0] uart_1_words_count = 8'd0;
wire uart_1_reset;
wire uart_1_wait;
wire uart_1_done;
reg [23:0] uart_1_count = 24'd10000000;
reg uart_1_is_ongoing = 1'd0;
reg dshot_0_storage = 1'd0;
reg dshot_0_re = 1'd0;
reg subfragments_rs232phytx0_state = 1'd0;
reg subfragments_rs232phytx0_next_state = 1'd0;
reg [3:0] basesoc_tx_count_rs232phytx0_next_value0 = 4'd0;
reg basesoc_tx_count_rs232phytx0_next_value_ce0 = 1'd0;
reg basesoc_serial_tx_rs232phytx0_next_value1 = 1'd0;
reg basesoc_serial_tx_rs232phytx0_next_value_ce1 = 1'd0;
reg [7:0] basesoc_tx_data_rs232phytx0_next_value2 = 8'd0;
reg basesoc_tx_data_rs232phytx0_next_value_ce2 = 1'd0;
reg subfragments_rs232phyrx0_state = 1'd0;
reg subfragments_rs232phyrx0_next_state = 1'd0;
reg [3:0] basesoc_rx_count_rs232phyrx0_next_value0 = 4'd0;
reg basesoc_rx_count_rs232phyrx0_next_value_ce0 = 1'd0;
reg [7:0] basesoc_rx_data_rs232phyrx0_next_value1 = 8'd0;
reg basesoc_rx_data_rs232phyrx0_next_value_ce1 = 1'd0;
wire subfragments_reset0;
wire subfragments_reset1;
wire subfragments_reset2;
wire subfragments_reset3;
wire subfragments_reset4;
wire subfragments_reset5;
wire subfragments_reset6;
wire subfragments_reset7;
wire subfragments_mmcm_fb;
reg subfragments_rs232phytx1_state = 1'd0;
reg subfragments_rs232phytx1_next_state = 1'd0;
reg [3:0] uart_1_phy_tx_count_rs232phytx1_next_value0 = 4'd0;
reg uart_1_phy_tx_count_rs232phytx1_next_value_ce0 = 1'd0;
reg tx_obj_rs232phytx1_next_value1 = 1'd0;
reg tx_obj_rs232phytx1_next_value_ce1 = 1'd0;
reg [7:0] uart_1_phy_tx_data_rs232phytx1_next_value2 = 8'd0;
reg uart_1_phy_tx_data_rs232phytx1_next_value_ce2 = 1'd0;
reg subfragments_rs232phyrx1_state = 1'd0;
reg subfragments_rs232phyrx1_next_state = 1'd0;
reg [3:0] uart_1_phy_rx_count_rs232phyrx1_next_value0 = 4'd0;
reg uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 = 1'd0;
reg [7:0] uart_1_phy_rx_data_rs232phyrx1_next_value1 = 8'd0;
reg uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 = 1'd0;
reg [2:0] subfragments_state = 3'd0;
reg [2:0] subfragments_next_state = 3'd0;
reg [1:0] uart_1_bytes_count_next_value0 = 2'd0;
reg uart_1_bytes_count_next_value_ce0 = 1'd0;
reg [7:0] uart_1_words_count_next_value1 = 8'd0;
reg uart_1_words_count_next_value_ce1 = 1'd0;
reg [7:0] uart_1_cmd_next_value2 = 8'd0;
reg uart_1_cmd_next_value_ce2 = 1'd0;
reg [7:0] uart_1_length_next_value3 = 8'd0;
reg uart_1_length_next_value_ce3 = 1'd0;
reg [31:0] uart_1_address_next_value4 = 32'd0;
reg uart_1_address_next_value_ce4 = 1'd0;
reg uart_1_incr_next_value5 = 1'd0;
reg uart_1_incr_next_value_ce5 = 1'd0;
reg [31:0] uart_1_data_next_value6 = 32'd0;
reg uart_1_data_next_value_ce6 = 1'd0;
reg [13:0] basesoc_basesoc_adr = 14'd0;
reg basesoc_basesoc_we = 1'd0;
reg [31:0] basesoc_basesoc_dat_w = 32'd0;
wire [31:0] basesoc_basesoc_dat_r;
wire [29:0] basesoc_basesoc_wishbone_adr;
wire [31:0] basesoc_basesoc_wishbone_dat_w;
reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0;
wire [3:0] basesoc_basesoc_wishbone_sel;
wire basesoc_basesoc_wishbone_cyc;
wire basesoc_basesoc_wishbone_stb;
reg basesoc_basesoc_wishbone_ack = 1'd0;
wire basesoc_basesoc_wishbone_we;
wire [2:0] basesoc_basesoc_wishbone_cti;
wire [1:0] basesoc_basesoc_wishbone_bte;
reg basesoc_basesoc_wishbone_err = 1'd0;
wire [29:0] basesoc_shared_adr;
wire [31:0] basesoc_shared_dat_w;
reg [31:0] basesoc_shared_dat_r = 32'd0;
wire [3:0] basesoc_shared_sel;
wire basesoc_shared_cyc;
wire basesoc_shared_stb;
reg basesoc_shared_ack = 1'd0;
wire basesoc_shared_we;
wire [2:0] basesoc_shared_cti;
wire [1:0] basesoc_shared_bte;
wire basesoc_shared_err;
wire [2:0] basesoc_request;
reg [1:0] basesoc_grant = 2'd0;
reg [2:0] basesoc_slave_sel = 3'd0;
reg [2:0] basesoc_slave_sel_r = 3'd0;
reg basesoc_error = 1'd0;
wire basesoc_wait;
wire basesoc_done;
reg [19:0] basesoc_count = 20'd1000000;
wire [13:0] basesoc_csr_bankarray_interface0_bank_bus_adr;
wire basesoc_csr_bankarray_interface0_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank0_in_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank0_in_r;
reg basesoc_csr_bankarray_csrbank0_in_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank0_in_w;
wire basesoc_csr_bankarray_csrbank0_sel;
wire [13:0] basesoc_csr_bankarray_interface1_bank_bus_adr;
wire basesoc_csr_bankarray_interface1_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank1_reset0_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_r;
reg basesoc_csr_bankarray_csrbank1_reset0_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_w;
reg basesoc_csr_bankarray_csrbank1_scratch0_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_r;
reg basesoc_csr_bankarray_csrbank1_scratch0_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_w;
reg basesoc_csr_bankarray_csrbank1_bus_errors_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_r;
reg basesoc_csr_bankarray_csrbank1_bus_errors_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_w;
wire basesoc_csr_bankarray_csrbank1_sel;
wire [13:0] basesoc_csr_bankarray_interface2_bank_bus_adr;
wire basesoc_csr_bankarray_interface2_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank2_id1_re = 1'd0;
wire [24:0] basesoc_csr_bankarray_csrbank2_id1_r;
reg basesoc_csr_bankarray_csrbank2_id1_we = 1'd0;
wire [24:0] basesoc_csr_bankarray_csrbank2_id1_w;
reg basesoc_csr_bankarray_csrbank2_id0_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank2_id0_r;
reg basesoc_csr_bankarray_csrbank2_id0_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank2_id0_w;
wire basesoc_csr_bankarray_csrbank2_sel;
wire [13:0] basesoc_csr_bankarray_interface3_bank_bus_adr;
wire basesoc_csr_bankarray_interface3_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank3_out0_re = 1'd0;
wire basesoc_csr_bankarray_csrbank3_out0_r;
reg basesoc_csr_bankarray_csrbank3_out0_we = 1'd0;
wire basesoc_csr_bankarray_csrbank3_out0_w;
wire basesoc_csr_bankarray_csrbank3_sel;
wire [13:0] basesoc_csr_bankarray_interface4_bank_bus_adr;
wire basesoc_csr_bankarray_interface4_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank4_w0_re = 1'd0;
wire [2:0] basesoc_csr_bankarray_csrbank4_w0_r;
reg basesoc_csr_bankarray_csrbank4_w0_we = 1'd0;
wire [2:0] basesoc_csr_bankarray_csrbank4_w0_w;
reg basesoc_csr_bankarray_csrbank4_r_re = 1'd0;
wire basesoc_csr_bankarray_csrbank4_r_r;
reg basesoc_csr_bankarray_csrbank4_r_we = 1'd0;
wire basesoc_csr_bankarray_csrbank4_r_w;
wire basesoc_csr_bankarray_csrbank4_sel;
wire [13:0] basesoc_csr_bankarray_sram_bus_adr;
wire basesoc_csr_bankarray_sram_bus_we;
wire [31:0] basesoc_csr_bankarray_sram_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_sram_bus_dat_r = 32'd0;
wire [4:0] basesoc_csr_bankarray_adr;
wire [7:0] basesoc_csr_bankarray_dat_r;
wire basesoc_csr_bankarray_sel;
reg basesoc_csr_bankarray_sel_r = 1'd0;
wire [13:0] basesoc_csr_bankarray_interface5_bank_bus_adr;
wire basesoc_csr_bankarray_interface5_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank5_out0_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank5_out0_r;
reg basesoc_csr_bankarray_csrbank5_out0_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank5_out0_w;
wire basesoc_csr_bankarray_csrbank5_sel;
wire [13:0] basesoc_csr_bankarray_interface6_bank_bus_adr;
wire basesoc_csr_bankarray_interface6_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank6_load0_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_load0_r;
reg basesoc_csr_bankarray_csrbank6_load0_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_load0_w;
reg basesoc_csr_bankarray_csrbank6_reload0_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_r;
reg basesoc_csr_bankarray_csrbank6_reload0_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_w;
reg basesoc_csr_bankarray_csrbank6_en0_re = 1'd0;
wire basesoc_csr_bankarray_csrbank6_en0_r;
reg basesoc_csr_bankarray_csrbank6_en0_we = 1'd0;
wire basesoc_csr_bankarray_csrbank6_en0_w;
reg basesoc_csr_bankarray_csrbank6_update_value0_re = 1'd0;
wire basesoc_csr_bankarray_csrbank6_update_value0_r;
reg basesoc_csr_bankarray_csrbank6_update_value0_we = 1'd0;
wire basesoc_csr_bankarray_csrbank6_update_value0_w;
reg basesoc_csr_bankarray_csrbank6_value_re = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_value_r;
reg basesoc_csr_bankarray_csrbank6_value_we = 1'd0;
wire [31:0] basesoc_csr_bankarray_csrbank6_value_w;
reg basesoc_csr_bankarray_csrbank6_ev_status_re = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_status_r;
reg basesoc_csr_bankarray_csrbank6_ev_status_we = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_status_w;
reg basesoc_csr_bankarray_csrbank6_ev_pending_re = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_pending_r;
reg basesoc_csr_bankarray_csrbank6_ev_pending_we = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_pending_w;
reg basesoc_csr_bankarray_csrbank6_ev_enable0_re = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_enable0_r;
reg basesoc_csr_bankarray_csrbank6_ev_enable0_we = 1'd0;
wire basesoc_csr_bankarray_csrbank6_ev_enable0_w;
wire basesoc_csr_bankarray_csrbank6_sel;
wire [13:0] basesoc_csr_bankarray_interface7_bank_bus_adr;
wire basesoc_csr_bankarray_interface7_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank7_txfull_re = 1'd0;
wire basesoc_csr_bankarray_csrbank7_txfull_r;
reg basesoc_csr_bankarray_csrbank7_txfull_we = 1'd0;
wire basesoc_csr_bankarray_csrbank7_txfull_w;
reg basesoc_csr_bankarray_csrbank7_rxempty_re = 1'd0;
wire basesoc_csr_bankarray_csrbank7_rxempty_r;
reg basesoc_csr_bankarray_csrbank7_rxempty_we = 1'd0;
wire basesoc_csr_bankarray_csrbank7_rxempty_w;
reg basesoc_csr_bankarray_csrbank7_ev_status_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_r;
reg basesoc_csr_bankarray_csrbank7_ev_status_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_w;
reg basesoc_csr_bankarray_csrbank7_ev_pending_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_r;
reg basesoc_csr_bankarray_csrbank7_ev_pending_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_w;
reg basesoc_csr_bankarray_csrbank7_ev_enable0_re = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_r;
reg basesoc_csr_bankarray_csrbank7_ev_enable0_we = 1'd0;
wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_w;
reg basesoc_csr_bankarray_csrbank7_txempty_re = 1'd0;
wire basesoc_csr_bankarray_csrbank7_txempty_r;
reg basesoc_csr_bankarray_csrbank7_txempty_we = 1'd0;
wire basesoc_csr_bankarray_csrbank7_txempty_w;
reg basesoc_csr_bankarray_csrbank7_rxfull_re = 1'd0;
wire basesoc_csr_bankarray_csrbank7_rxfull_r;
reg basesoc_csr_bankarray_csrbank7_rxfull_we = 1'd0;
wire basesoc_csr_bankarray_csrbank7_rxfull_w;
wire basesoc_csr_bankarray_csrbank7_sel;
wire [13:0] basesoc_csr_bankarray_interface8_bank_bus_adr;
wire basesoc_csr_bankarray_interface8_bank_bus_we;
wire [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_w;
reg [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_r = 32'd0;
reg basesoc_csr_bankarray_csrbank8_temperature_re = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_r;
reg basesoc_csr_bankarray_csrbank8_temperature_we = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_w;
reg basesoc_csr_bankarray_csrbank8_vccint_re = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_r;
reg basesoc_csr_bankarray_csrbank8_vccint_we = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_w;
reg basesoc_csr_bankarray_csrbank8_vccaux_re = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_r;
reg basesoc_csr_bankarray_csrbank8_vccaux_we = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_w;
reg basesoc_csr_bankarray_csrbank8_vccbram_re = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_r;
reg basesoc_csr_bankarray_csrbank8_vccbram_we = 1'd0;
wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_w;
reg basesoc_csr_bankarray_csrbank8_eoc_re = 1'd0;
wire basesoc_csr_bankarray_csrbank8_eoc_r;
reg basesoc_csr_bankarray_csrbank8_eoc_we = 1'd0;
wire basesoc_csr_bankarray_csrbank8_eoc_w;
reg basesoc_csr_bankarray_csrbank8_eos_re = 1'd0;
wire basesoc_csr_bankarray_csrbank8_eos_r;
reg basesoc_csr_bankarray_csrbank8_eos_we = 1'd0;
wire basesoc_csr_bankarray_csrbank8_eos_w;
wire basesoc_csr_bankarray_csrbank8_sel;
wire [13:0] basesoc_csr_interconnect_adr;
wire basesoc_csr_interconnect_we;
wire [31:0] basesoc_csr_interconnect_dat_w;
wire [31:0] basesoc_csr_interconnect_dat_r;
reg basesoc_state = 1'd0;
reg basesoc_next_state = 1'd0;
reg [29:0] array_muxed0 = 30'd0;
reg [31:0] array_muxed1 = 32'd0;
reg [3:0] array_muxed2 = 4'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 3'd0;
reg [1:0] array_muxed7 = 2'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0;
wire xilinxasyncresetsynchronizerimpl0;
wire xilinxasyncresetsynchronizerimpl0_rst_meta;
wire xilinxasyncresetsynchronizerimpl1;
wire xilinxasyncresetsynchronizerimpl1_rst_meta;
wire xilinxasyncresetsynchronizerimpl1_expr;
wire xilinxasyncresetsynchronizerimpl2;
wire xilinxasyncresetsynchronizerimpl2_rst_meta;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs0 = 2'd0;
(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs1 = 2'd0;
wire xilinxmultiregimpl1;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0;
//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------
assign basesoc_reset = (basesoc_soc_rst | basesoc_cpu_rst);
assign crg_rst = basesoc_soc_rst;
assign basesoc_bus_error = basesoc_error;
always @(*) begin
basesoc_interrupt <= 32'd0;
basesoc_interrupt[1] <= basesoc_timer_irq;
basesoc_interrupt[0] <= basesoc_uart_irq;
end
assign basesoc_bus_errors_status = basesoc_bus_errors;
always @(*) begin
subfragments_rs232phytx0_next_state <= 1'd0;
basesoc_tx_count_rs232phytx0_next_value0 <= 4'd0;
basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd0;
basesoc_tx_sink_ready <= 1'd0;
basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0;
basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd0;
basesoc_tx_data_rs232phytx0_next_value2 <= 8'd0;
basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd0;
basesoc_tx_enable <= 1'd0;
subfragments_rs232phytx0_next_state <= subfragments_rs232phytx0_state;
case (subfragments_rs232phytx0_state)
1'd1: begin
basesoc_tx_enable <= 1'd1;
if (basesoc_tx_tick) begin
basesoc_serial_tx_rs232phytx0_next_value1 <= basesoc_tx_data;
basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1;
basesoc_tx_count_rs232phytx0_next_value0 <= (basesoc_tx_count + 1'd1);
basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1;
basesoc_tx_data_rs232phytx0_next_value2 <= {1'd1, basesoc_tx_data[7:1]};
basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1;
if ((basesoc_tx_count == 4'd9)) begin
basesoc_tx_sink_ready <= 1'd1;
subfragments_rs232phytx0_next_state <= 1'd0;
end
end
end
default: begin
basesoc_tx_count_rs232phytx0_next_value0 <= 1'd0;
basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1;
basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd1;
basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1;
if (basesoc_tx_sink_valid) begin
basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0;
basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1;
basesoc_tx_data_rs232phytx0_next_value2 <= basesoc_tx_sink_payload_data;
basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1;
subfragments_rs232phytx0_next_state <= 1'd1;
end
end
endcase
end
always @(*) begin
subfragments_rs232phyrx0_next_state <= 1'd0;
basesoc_rx_count_rs232phyrx0_next_value0 <= 4'd0;
basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd0;
basesoc_rx_source_valid <= 1'd0;
basesoc_rx_source_payload_data <= 8'd0;
basesoc_rx_data_rs232phyrx0_next_value1 <= 8'd0;
basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd0;
basesoc_rx_enable <= 1'd0;
subfragments_rs232phyrx0_next_state <= subfragments_rs232phyrx0_state;
case (subfragments_rs232phyrx0_state)
1'd1: begin
basesoc_rx_enable <= 1'd1;
if (basesoc_rx_tick) begin
basesoc_rx_count_rs232phyrx0_next_value0 <= (basesoc_rx_count + 1'd1);
basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1;
basesoc_rx_data_rs232phyrx0_next_value1 <= {basesoc_rx_rx, basesoc_rx_data[7:1]};
basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd1;
if ((basesoc_rx_count == 4'd9)) begin
basesoc_rx_source_valid <= (basesoc_rx_rx == 1'd1);
basesoc_rx_source_payload_data <= basesoc_rx_data;
subfragments_rs232phyrx0_next_state <= 1'd0;
end
end
end
default: begin
basesoc_rx_count_rs232phyrx0_next_value0 <= 1'd0;
basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1;
if (((basesoc_rx_rx == 1'd0) & (basesoc_rx_rx_d == 1'd1))) begin
subfragments_rs232phyrx0_next_state <= 1'd1;
end
end
endcase
end
assign basesoc_uart_uart_sink_valid = basesoc_rx_source_valid;
assign basesoc_rx_source_ready = basesoc_uart_uart_sink_ready;
assign basesoc_uart_uart_sink_first = basesoc_rx_source_first;
assign basesoc_uart_uart_sink_last = basesoc_rx_source_last;
assign basesoc_uart_uart_sink_payload_data = basesoc_rx_source_payload_data;
assign basesoc_tx_sink_valid = basesoc_uart_uart_source_valid;
assign basesoc_uart_uart_source_ready = basesoc_tx_sink_ready;
assign basesoc_tx_sink_first = basesoc_uart_uart_source_first;
assign basesoc_tx_sink_last = basesoc_uart_uart_source_last;
assign basesoc_tx_sink_payload_data = basesoc_uart_uart_source_payload_data;
assign basesoc_uart_tx_fifo_sink_valid = basesoc_uart_rxtx_re;
assign basesoc_uart_tx_fifo_sink_payload_data = basesoc_uart_rxtx_r;
assign basesoc_uart_uart_source_valid = basesoc_uart_tx_fifo_source_valid;
assign basesoc_uart_tx_fifo_source_ready = basesoc_uart_uart_source_ready;
assign basesoc_uart_uart_source_first = basesoc_uart_tx_fifo_source_first;
assign basesoc_uart_uart_source_last = basesoc_uart_tx_fifo_source_last;
assign basesoc_uart_uart_source_payload_data = basesoc_uart_tx_fifo_source_payload_data;
assign basesoc_uart_txfull_status = (~basesoc_uart_tx_fifo_sink_ready);
assign basesoc_uart_txempty_status = (~basesoc_uart_tx_fifo_source_valid);
assign basesoc_uart_tx_trigger = basesoc_uart_tx_fifo_sink_ready;
assign basesoc_uart_rx_fifo_sink_valid = basesoc_uart_uart_sink_valid;
assign basesoc_uart_uart_sink_ready = basesoc_uart_rx_fifo_sink_ready;
assign basesoc_uart_rx_fifo_sink_first = basesoc_uart_uart_sink_first;
assign basesoc_uart_rx_fifo_sink_last = basesoc_uart_uart_sink_last;
assign basesoc_uart_rx_fifo_sink_payload_data = basesoc_uart_uart_sink_payload_data;
assign basesoc_uart_rxtx_w = basesoc_uart_rx_fifo_source_payload_data;
assign basesoc_uart_rx_fifo_source_ready = (basesoc_uart_rx_clear | (1'd0 & basesoc_uart_rxtx_we));
assign basesoc_uart_rxempty_status = (~basesoc_uart_rx_fifo_source_valid);
assign basesoc_uart_rxfull_status = (~basesoc_uart_rx_fifo_sink_ready);
assign basesoc_uart_rx_trigger = basesoc_uart_rx_fifo_source_valid;
assign basesoc_uart_tx0 = basesoc_uart_tx_status;
assign basesoc_uart_tx1 = basesoc_uart_tx_pending;
always @(*) begin
basesoc_uart_tx_clear <= 1'd0;
if ((basesoc_uart_pending_re & basesoc_uart_pending_r[0])) begin
basesoc_uart_tx_clear <= 1'd1;
end
end
assign basesoc_uart_rx0 = basesoc_uart_rx_status;
assign basesoc_uart_rx1 = basesoc_uart_rx_pending;
always @(*) begin
basesoc_uart_rx_clear <= 1'd0;
if ((basesoc_uart_pending_re & basesoc_uart_pending_r[1])) begin
basesoc_uart_rx_clear <= 1'd1;
end
end
assign basesoc_uart_irq = ((basesoc_uart_pending_status[0] & basesoc_uart_enable_storage[0]) | (basesoc_uart_pending_status[1] & basesoc_uart_enable_storage[1]));
assign basesoc_uart_tx_status = basesoc_uart_tx_trigger;
assign basesoc_uart_rx_status = basesoc_uart_rx_trigger;
assign basesoc_uart_tx_fifo_syncfifo_din = {basesoc_uart_tx_fifo_fifo_in_last, basesoc_uart_tx_fifo_fifo_in_first, basesoc_uart_tx_fifo_fifo_in_payload_data};
assign {basesoc_uart_tx_fifo_fifo_out_last, basesoc_uart_tx_fifo_fifo_out_first, basesoc_uart_tx_fifo_fifo_out_payload_data} = basesoc_uart_tx_fifo_syncfifo_dout;
assign basesoc_uart_tx_fifo_sink_ready = basesoc_uart_tx_fifo_syncfifo_writable;
assign basesoc_uart_tx_fifo_syncfifo_we = basesoc_uart_tx_fifo_sink_valid;
assign basesoc_uart_tx_fifo_fifo_in_first = basesoc_uart_tx_fifo_sink_first;
assign basesoc_uart_tx_fifo_fifo_in_last = basesoc_uart_tx_fifo_sink_last;
assign basesoc_uart_tx_fifo_fifo_in_payload_data = basesoc_uart_tx_fifo_sink_payload_data;
assign basesoc_uart_tx_fifo_source_valid = basesoc_uart_tx_fifo_readable;
assign basesoc_uart_tx_fifo_source_first = basesoc_uart_tx_fifo_fifo_out_first;
assign basesoc_uart_tx_fifo_source_last = basesoc_uart_tx_fifo_fifo_out_last;
assign basesoc_uart_tx_fifo_source_payload_data = basesoc_uart_tx_fifo_fifo_out_payload_data;
assign basesoc_uart_tx_fifo_re = basesoc_uart_tx_fifo_source_ready;
assign basesoc_uart_tx_fifo_syncfifo_re = (basesoc_uart_tx_fifo_syncfifo_readable & ((~basesoc_uart_tx_fifo_readable) | basesoc_uart_tx_fifo_re));
assign basesoc_uart_tx_fifo_level1 = (basesoc_uart_tx_fifo_level0 + basesoc_uart_tx_fifo_readable);
always @(*) begin
basesoc_uart_tx_fifo_wrport_adr <= 4'd0;
if (basesoc_uart_tx_fifo_replace) begin
basesoc_uart_tx_fifo_wrport_adr <= (basesoc_uart_tx_fifo_produce - 1'd1);
end else begin
basesoc_uart_tx_fifo_wrport_adr <= basesoc_uart_tx_fifo_produce;
end
end
assign basesoc_uart_tx_fifo_wrport_dat_w = basesoc_uart_tx_fifo_syncfifo_din;
assign basesoc_uart_tx_fifo_wrport_we = (basesoc_uart_tx_fifo_syncfifo_we & (basesoc_uart_tx_fifo_syncfifo_writable | basesoc_uart_tx_fifo_replace));
assign basesoc_uart_tx_fifo_do_read = (basesoc_uart_tx_fifo_syncfifo_readable & basesoc_uart_tx_fifo_syncfifo_re);
assign basesoc_uart_tx_fifo_rdport_adr = basesoc_uart_tx_fifo_consume;
assign basesoc_uart_tx_fifo_syncfifo_dout = basesoc_uart_tx_fifo_rdport_dat_r;
assign basesoc_uart_tx_fifo_rdport_re = basesoc_uart_tx_fifo_do_read;
assign basesoc_uart_tx_fifo_syncfifo_writable = (basesoc_uart_tx_fifo_level0 != 5'd16);
assign basesoc_uart_tx_fifo_syncfifo_readable = (basesoc_uart_tx_fifo_level0 != 1'd0);
assign basesoc_uart_rx_fifo_syncfifo_din = {basesoc_uart_rx_fifo_fifo_in_last, basesoc_uart_rx_fifo_fifo_in_first, basesoc_uart_rx_fifo_fifo_in_payload_data};
assign {basesoc_uart_rx_fifo_fifo_out_last, basesoc_uart_rx_fifo_fifo_out_first, basesoc_uart_rx_fifo_fifo_out_payload_data} = basesoc_uart_rx_fifo_syncfifo_dout;
assign basesoc_uart_rx_fifo_sink_ready = basesoc_uart_rx_fifo_syncfifo_writable;
assign basesoc_uart_rx_fifo_syncfifo_we = basesoc_uart_rx_fifo_sink_valid;
assign basesoc_uart_rx_fifo_fifo_in_first = basesoc_uart_rx_fifo_sink_first;
assign basesoc_uart_rx_fifo_fifo_in_last = basesoc_uart_rx_fifo_sink_last;
assign basesoc_uart_rx_fifo_fifo_in_payload_data = basesoc_uart_rx_fifo_sink_payload_data;
assign basesoc_uart_rx_fifo_source_valid = basesoc_uart_rx_fifo_readable;
assign basesoc_uart_rx_fifo_source_first = basesoc_uart_rx_fifo_fifo_out_first;
assign basesoc_uart_rx_fifo_source_last = basesoc_uart_rx_fifo_fifo_out_last;
assign basesoc_uart_rx_fifo_source_payload_data = basesoc_uart_rx_fifo_fifo_out_payload_data;
assign basesoc_uart_rx_fifo_re = basesoc_uart_rx_fifo_source_ready;
assign basesoc_uart_rx_fifo_syncfifo_re = (basesoc_uart_rx_fifo_syncfifo_readable & ((~basesoc_uart_rx_fifo_readable) | basesoc_uart_rx_fifo_re));
assign basesoc_uart_rx_fifo_level1 = (basesoc_uart_rx_fifo_level0 + basesoc_uart_rx_fifo_readable);
always @(*) begin
basesoc_uart_rx_fifo_wrport_adr <= 4'd0;
if (basesoc_uart_rx_fifo_replace) begin
basesoc_uart_rx_fifo_wrport_adr <= (basesoc_uart_rx_fifo_produce - 1'd1);
end else begin
basesoc_uart_rx_fifo_wrport_adr <= basesoc_uart_rx_fifo_produce;
end
end
assign basesoc_uart_rx_fifo_wrport_dat_w = basesoc_uart_rx_fifo_syncfifo_din;
assign basesoc_uart_rx_fifo_wrport_we = (basesoc_uart_rx_fifo_syncfifo_we & (basesoc_uart_rx_fifo_syncfifo_writable | basesoc_uart_rx_fifo_replace));
assign basesoc_uart_rx_fifo_do_read = (basesoc_uart_rx_fifo_syncfifo_readable & basesoc_uart_rx_fifo_syncfifo_re);
assign basesoc_uart_rx_fifo_rdport_adr = basesoc_uart_rx_fifo_consume;
assign basesoc_uart_rx_fifo_syncfifo_dout = basesoc_uart_rx_fifo_rdport_dat_r;
assign basesoc_uart_rx_fifo_rdport_re = basesoc_uart_rx_fifo_do_read;
assign basesoc_uart_rx_fifo_syncfifo_writable = (basesoc_uart_rx_fifo_level0 != 5'd16);
assign basesoc_uart_rx_fifo_syncfifo_readable = (basesoc_uart_rx_fifo_level0 != 1'd0);
assign basesoc_timer_zero_trigger = (basesoc_timer_value == 1'd0);
assign basesoc_timer_zero0 = basesoc_timer_zero_status;
assign basesoc_timer_zero1 = basesoc_timer_zero_pending;
always @(*) begin
basesoc_timer_zero_clear <= 1'd0;
if ((basesoc_timer_pending_re & basesoc_timer_pending_r)) begin
basesoc_timer_zero_clear <= 1'd1;
end
end
assign basesoc_timer_irq = (basesoc_timer_pending_status & basesoc_timer_enable_storage);
assign basesoc_timer_zero_status = basesoc_timer_zero_trigger;
assign crg_reset = crg_rst;
assign crg_clkin = clk12;
assign sys_clk = crg_clkout_buf0;
assign sys2x_clk = crg_clkout_buf1;
assign idelay_clk = crg_clkout_buf2;
assign directory0_w = csrstorage0_storage;
assign csr_08000_w = csrstorage1_storage;
assign basesoc_adr = basesoc_ram_bus_adr[13:0];
assign basesoc_ram_bus_dat_r = basesoc_dat_r;
assign dna_clk = dna_count[0];
always @(*) begin
xadc_den <= 1'd0;
xadc_dadr <= 7'd0;
if ((~xadc_drp_en)) begin
xadc_den <= xadc_eoc;
xadc_dadr <= xadc_channel;
end
end
assign leds_wait = (~leds_done);
always @(*) begin
user_led1 <= 1'd0;
user_led0 <= 1'd0;
if ((leds_mode == 1'd1)) begin
{user_led1, user_led0} <= leds_storage;
end else begin
{user_led1, user_led0} <= leds_chaser;
end
end
assign leds_done = (leds_count == 1'd0);
always @(*) begin
subfragments_rs232phytx1_next_state <= 1'd0;
uart_1_phy_tx_count_rs232phytx1_next_value0 <= 4'd0;
uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd0;
uart_1_phy_tx_enable <= 1'd0;
tx_obj_rs232phytx1_next_value1 <= 1'd0;
tx_obj_rs232phytx1_next_value_ce1 <= 1'd0;
uart_1_phy_tx_data_rs232phytx1_next_value2 <= 8'd0;
uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd0;
uart_1_phy_tx_sink_ready <= 1'd0;
subfragments_rs232phytx1_next_state <= subfragments_rs232phytx1_state;
case (subfragments_rs232phytx1_state)
1'd1: begin
uart_1_phy_tx_enable <= 1'd1;
if (uart_1_phy_tx_tick) begin
tx_obj_rs232phytx1_next_value1 <= uart_1_phy_tx_data;
tx_obj_rs232phytx1_next_value_ce1 <= 1'd1;
uart_1_phy_tx_count_rs232phytx1_next_value0 <= (uart_1_phy_tx_count + 1'd1);
uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1;
uart_1_phy_tx_data_rs232phytx1_next_value2 <= {1'd1, uart_1_phy_tx_data[7:1]};
uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1;
if ((uart_1_phy_tx_count == 4'd9)) begin
uart_1_phy_tx_sink_ready <= 1'd1;
subfragments_rs232phytx1_next_state <= 1'd0;
end
end
end
default: begin
uart_1_phy_tx_count_rs232phytx1_next_value0 <= 1'd0;
uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1;
tx_obj_rs232phytx1_next_value1 <= 1'd1;
tx_obj_rs232phytx1_next_value_ce1 <= 1'd1;
if (uart_1_phy_tx_sink_valid) begin
tx_obj_rs232phytx1_next_value1 <= 1'd0;
tx_obj_rs232phytx1_next_value_ce1 <= 1'd1;
uart_1_phy_tx_data_rs232phytx1_next_value2 <= uart_1_phy_tx_sink_payload_data;
uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1;
subfragments_rs232phytx1_next_state <= 1'd1;
end
end
endcase
end
always @(*) begin
uart_1_phy_rx_source_payload_data <= 8'd0;
subfragments_rs232phyrx1_next_state <= 1'd0;
uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 4'd0;
uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd0;
uart_1_phy_rx_enable <= 1'd0;
uart_1_phy_rx_data_rs232phyrx1_next_value1 <= 8'd0;
uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd0;
uart_1_phy_rx_source_valid <= 1'd0;
subfragments_rs232phyrx1_next_state <= subfragments_rs232phyrx1_state;
case (subfragments_rs232phyrx1_state)
1'd1: begin
uart_1_phy_rx_enable <= 1'd1;
if (uart_1_phy_rx_tick) begin
uart_1_phy_rx_count_rs232phyrx1_next_value0 <= (uart_1_phy_rx_count + 1'd1);
uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1;
uart_1_phy_rx_data_rs232phyrx1_next_value1 <= {uart_1_phy_rx_rx, uart_1_phy_rx_data[7:1]};
uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd1;
if ((uart_1_phy_rx_count == 4'd9)) begin
uart_1_phy_rx_source_valid <= (uart_1_phy_rx_rx == 1'd1);
uart_1_phy_rx_source_payload_data <= uart_1_phy_rx_data;
subfragments_rs232phyrx1_next_state <= 1'd0;
end
end
end
default: begin
uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 1'd0;
uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1;
if (((uart_1_phy_rx_rx == 1'd0) & (uart_1_phy_rx_rx_d == 1'd1))) begin
subfragments_rs232phyrx1_next_state <= 1'd1;
end
end
endcase
end
assign uart_1_wait = (~uart_1_is_ongoing);
assign uart_1_reset = uart_1_done;
assign uart_1_wishbone_adr = uart_1_address;
assign uart_1_wishbone_dat_w = uart_1_data;
assign uart_1_wishbone_sel = 4'd15;
always @(*) begin
uart_1_phy_tx_sink_payload_data <= 8'd0;
case (uart_1_bytes_count)
1'd0: begin
uart_1_phy_tx_sink_payload_data <= uart_1_data[31:24];
end
1'd1: begin
uart_1_phy_tx_sink_payload_data <= uart_1_data[31:16];
end
2'd2: begin
uart_1_phy_tx_sink_payload_data <= uart_1_data[31:8];
end
2'd3: begin
uart_1_phy_tx_sink_payload_data <= uart_1_data[31:0];
end
endcase
end
assign uart_1_phy_tx_sink_last = ((uart_1_bytes_count == 2'd3) & (uart_1_words_count == (uart_1_length - 1'd1)));
always @(*) begin
subfragments_next_state <= 3'd0;
uart_1_bytes_count_next_value0 <= 2'd0;
uart_1_bytes_count_next_value_ce0 <= 1'd0;
uart_1_words_count_next_value1 <= 8'd0;
uart_1_words_count_next_value_ce1 <= 1'd0;
uart_1_cmd_next_value2 <= 8'd0;
uart_1_cmd_next_value_ce2 <= 1'd0;
uart_1_length_next_value3 <= 8'd0;
uart_1_length_next_value_ce3 <= 1'd0;
uart_1_phy_tx_sink_valid <= 1'd0;
uart_1_address_next_value4 <= 32'd0;
uart_1_address_next_value_ce4 <= 1'd0;
uart_1_is_ongoing <= 1'd0;
uart_1_incr_next_value5 <= 1'd0;
uart_1_incr_next_value_ce5 <= 1'd0;
uart_1_wishbone_cyc <= 1'd0;
uart_1_data_next_value6 <= 32'd0;
uart_1_wishbone_stb <= 1'd0;
uart_1_data_next_value_ce6 <= 1'd0;
uart_1_wishbone_we <= 1'd0;
uart_1_phy_rx_source_ready <= 1'd0;
subfragments_next_state <= subfragments_state;
case (subfragments_state)
1'd1: begin
uart_1_phy_rx_source_ready <= 1'd1;
if (uart_1_phy_rx_source_valid) begin
uart_1_length_next_value3 <= uart_1_phy_rx_source_payload_data;
uart_1_length_next_value_ce3 <= 1'd1;
subfragments_next_state <= 2'd2;
end
end
2'd2: begin
uart_1_phy_rx_source_ready <= 1'd1;
if (uart_1_phy_rx_source_valid) begin
uart_1_address_next_value4 <= {uart_1_address, uart_1_phy_rx_source_payload_data};
uart_1_address_next_value_ce4 <= 1'd1;
uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1);
uart_1_bytes_count_next_value_ce0 <= 1'd1;
if ((uart_1_bytes_count == 2'd3)) begin
if (((uart_1_cmd == 1'd1) | (uart_1_cmd == 2'd3))) begin
uart_1_incr_next_value5 <= (uart_1_cmd == 1'd1);
uart_1_incr_next_value_ce5 <= 1'd1;
subfragments_next_state <= 2'd3;
end else begin
if (((uart_1_cmd == 2'd2) | (uart_1_cmd == 3'd4))) begin
uart_1_incr_next_value5 <= (uart_1_cmd == 2'd2);
uart_1_incr_next_value_ce5 <= 1'd1;
subfragments_next_state <= 3'd5;
end else begin
subfragments_next_state <= 1'd0;
end
end
end
end
end
2'd3: begin
uart_1_phy_rx_source_ready <= 1'd1;
if (uart_1_phy_rx_source_valid) begin
uart_1_data_next_value6 <= {uart_1_data, uart_1_phy_rx_source_payload_data};
uart_1_data_next_value_ce6 <= 1'd1;
uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1);
uart_1_bytes_count_next_value_ce0 <= 1'd1;
if ((uart_1_bytes_count == 2'd3)) begin
subfragments_next_state <= 3'd4;
end
end
end
3'd4: begin
uart_1_phy_rx_source_ready <= 1'd0;
uart_1_wishbone_stb <= 1'd1;
uart_1_wishbone_we <= 1'd1;
uart_1_wishbone_cyc <= 1'd1;
if (uart_1_wishbone_ack) begin
uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1);
uart_1_words_count_next_value_ce1 <= 1'd1;
uart_1_address_next_value4 <= (uart_1_address + uart_1_incr);
uart_1_address_next_value_ce4 <= 1'd1;
if ((uart_1_words_count == (uart_1_length - 1'd1))) begin
subfragments_next_state <= 1'd0;
end else begin
subfragments_next_state <= 2'd3;
end
end
end
3'd5: begin
uart_1_phy_rx_source_ready <= 1'd0;
uart_1_wishbone_stb <= 1'd1;
uart_1_wishbone_we <= 1'd0;
uart_1_wishbone_cyc <= 1'd1;
if (uart_1_wishbone_ack) begin
uart_1_data_next_value6 <= uart_1_wishbone_dat_r;
uart_1_data_next_value_ce6 <= 1'd1;
subfragments_next_state <= 3'd6;
end
end
3'd6: begin
uart_1_phy_rx_source_ready <= 1'd0;
uart_1_phy_tx_sink_valid <= 1'd1;
if (uart_1_phy_tx_sink_ready) begin
uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1);
uart_1_bytes_count_next_value_ce0 <= 1'd1;
if ((uart_1_bytes_count == 2'd3)) begin
uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1);
uart_1_words_count_next_value_ce1 <= 1'd1;
uart_1_address_next_value4 <= (uart_1_address + uart_1_incr);
uart_1_address_next_value_ce4 <= 1'd1;
if ((uart_1_words_count == (uart_1_length - 1'd1))) begin
subfragments_next_state <= 1'd0;
end else begin
subfragments_next_state <= 3'd5;
end
end
end
end
default: begin
uart_1_is_ongoing <= 1'd1;
uart_1_phy_rx_source_ready <= 1'd1;
uart_1_bytes_count_next_value0 <= 1'd0;
uart_1_bytes_count_next_value_ce0 <= 1'd1;
uart_1_words_count_next_value1 <= 1'd0;
uart_1_words_count_next_value_ce1 <= 1'd1;
if (uart_1_phy_rx_source_valid) begin
uart_1_cmd_next_value2 <= uart_1_phy_rx_source_payload_data;
uart_1_cmd_next_value_ce2 <= 1'd1;
subfragments_next_state <= 1'd1;
end
end
endcase
end
assign uart_1_done = (uart_1_count == 1'd0);
assign digital43 = dshot_0_storage;
always @(*) begin
basesoc_basesoc_wishbone_dat_r <= 32'd0;
basesoc_basesoc_adr <= 14'd0;
basesoc_basesoc_we <= 1'd0;
basesoc_basesoc_dat_w <= 32'd0;
basesoc_basesoc_wishbone_ack <= 1'd0;
basesoc_next_state <= 1'd0;
basesoc_next_state <= basesoc_state;
case (basesoc_state)
1'd1: begin
basesoc_basesoc_wishbone_ack <= 1'd1;
basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r;
basesoc_next_state <= 1'd0;
end
default: begin
basesoc_basesoc_dat_w <= basesoc_basesoc_wishbone_dat_w;
if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin
basesoc_basesoc_adr <= basesoc_basesoc_wishbone_adr;
basesoc_basesoc_we <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0));
basesoc_next_state <= 1'd1;
end
end
endcase
end
assign basesoc_shared_adr = array_muxed0;
assign basesoc_shared_dat_w = array_muxed1;
assign basesoc_shared_sel = array_muxed2;
assign basesoc_shared_cyc = array_muxed3;
assign basesoc_shared_stb = array_muxed4;
assign basesoc_shared_we = array_muxed5;
assign basesoc_shared_cti = array_muxed6;
assign basesoc_shared_bte = array_muxed7;
assign basesoc_ibus_dat_r = basesoc_shared_dat_r;
assign basesoc_dbus_dat_r = basesoc_shared_dat_r;
assign uart_1_wishbone_dat_r = basesoc_shared_dat_r;
assign basesoc_ibus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd0));
assign basesoc_dbus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd1));
assign uart_1_wishbone_ack = (basesoc_shared_ack & (basesoc_grant == 2'd2));
assign basesoc_ibus_err = (basesoc_shared_err & (basesoc_grant == 1'd0));
assign basesoc_dbus_err = (basesoc_shared_err & (basesoc_grant == 1'd1));
assign uart_1_wishbone_err = (basesoc_shared_err & (basesoc_grant == 2'd2));
assign basesoc_request = {uart_1_wishbone_cyc, basesoc_dbus_cyc, basesoc_ibus_cyc};
always @(*) begin
basesoc_slave_sel <= 3'd0;
basesoc_slave_sel[0] <= (basesoc_shared_adr[29:14] == 1'd0);
basesoc_slave_sel[1] <= (basesoc_shared_adr[29:17] == 2'd2);
basesoc_slave_sel[2] <= (basesoc_shared_adr[29:14] == 16'd65520);
end
assign basesoc_ram_bus_adr = basesoc_shared_adr;
assign basesoc_ram_bus_dat_w = basesoc_shared_dat_w;
assign basesoc_ram_bus_sel = basesoc_shared_sel;
assign basesoc_ram_bus_stb = basesoc_shared_stb;
assign basesoc_ram_bus_we = basesoc_shared_we;
assign basesoc_ram_bus_cti = basesoc_shared_cti;
assign basesoc_ram_bus_bte = basesoc_shared_bte;
assign sram_bus_adr = basesoc_shared_adr;
assign sram_bus_dat_w = basesoc_shared_dat_w;
assign sram_bus_sel = basesoc_shared_sel;
assign sram_bus_stb = basesoc_shared_stb;
assign sram_bus_we = basesoc_shared_we;
assign sram_bus_cti = basesoc_shared_cti;
assign sram_bus_bte = basesoc_shared_bte;
assign basesoc_basesoc_wishbone_adr = basesoc_shared_adr;
assign basesoc_basesoc_wishbone_dat_w = basesoc_shared_dat_w;
assign basesoc_basesoc_wishbone_sel = basesoc_shared_sel;
assign basesoc_basesoc_wishbone_stb = basesoc_shared_stb;
assign basesoc_basesoc_wishbone_we = basesoc_shared_we;
assign basesoc_basesoc_wishbone_cti = basesoc_shared_cti;
assign basesoc_basesoc_wishbone_bte = basesoc_shared_bte;
assign basesoc_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[0]);
assign sram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[1]);
assign basesoc_basesoc_wishbone_cyc = (basesoc_shared_cyc & basesoc_slave_sel[2]);
assign basesoc_shared_err = ((basesoc_ram_bus_err | sram_bus_err) | basesoc_basesoc_wishbone_err);
assign basesoc_wait = ((basesoc_shared_stb & basesoc_shared_cyc) & (~basesoc_shared_ack));
always @(*) begin
basesoc_shared_ack <= 1'd0;
basesoc_shared_dat_r <= 32'd0;
basesoc_error <= 1'd0;
basesoc_shared_ack <= ((basesoc_ram_bus_ack | sram_bus_ack) | basesoc_basesoc_wishbone_ack);
basesoc_shared_dat_r <= ((({32{basesoc_slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{basesoc_slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{basesoc_slave_sel_r[2]}} & basesoc_basesoc_wishbone_dat_r));
if (basesoc_done) begin
basesoc_shared_dat_r <= 32'd4294967295;
basesoc_shared_ack <= 1'd1;
basesoc_error <= 1'd1;
end
end
assign basesoc_done = (basesoc_count == 1'd0);
assign basesoc_csr_bankarray_csrbank0_sel = (basesoc_csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4);
assign basesoc_csr_bankarray_csrbank0_in_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank0_in_re <= 1'd0;
basesoc_csr_bankarray_csrbank0_in_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank0_sel & (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank0_in_re <= basesoc_csr_bankarray_interface0_bank_bus_we;
basesoc_csr_bankarray_csrbank0_in_we <= (~basesoc_csr_bankarray_interface0_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank0_in_w = buttons_status[1:0];
assign buttons_we = basesoc_csr_bankarray_csrbank0_in_we;
assign basesoc_csr_bankarray_csrbank1_sel = (basesoc_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd7);
assign basesoc_csr_bankarray_csrbank1_reset0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank1_reset0_re <= 1'd0;
basesoc_csr_bankarray_csrbank1_reset0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank1_reset0_re <= basesoc_csr_bankarray_interface1_bank_bus_we;
basesoc_csr_bankarray_csrbank1_reset0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank1_scratch0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank1_scratch0_we <= 1'd0;
basesoc_csr_bankarray_csrbank1_scratch0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank1_scratch0_re <= basesoc_csr_bankarray_interface1_bank_bus_we;
basesoc_csr_bankarray_csrbank1_scratch0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank1_bus_errors_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank1_bus_errors_re <= 1'd0;
basesoc_csr_bankarray_csrbank1_bus_errors_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin
basesoc_csr_bankarray_csrbank1_bus_errors_re <= basesoc_csr_bankarray_interface1_bank_bus_we;
basesoc_csr_bankarray_csrbank1_bus_errors_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we);
end
end
always @(*) begin
basesoc_soc_rst <= 1'd0;
if (basesoc_reset_re) begin
basesoc_soc_rst <= basesoc_reset_storage[0];
end
end
assign basesoc_cpu_rst = basesoc_reset_storage[1];
assign basesoc_csr_bankarray_csrbank1_reset0_w = basesoc_reset_storage[1:0];
assign basesoc_csr_bankarray_csrbank1_scratch0_w = basesoc_scratch_storage[31:0];
assign basesoc_csr_bankarray_csrbank1_bus_errors_w = basesoc_bus_errors_status[31:0];
assign basesoc_bus_errors_we = basesoc_csr_bankarray_csrbank1_bus_errors_we;
assign basesoc_csr_bankarray_csrbank2_sel = (basesoc_csr_bankarray_interface2_bank_bus_adr[13:9] == 1'd1);
assign basesoc_csr_bankarray_csrbank2_id1_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[24:0];
always @(*) begin
basesoc_csr_bankarray_csrbank2_id1_we <= 1'd0;
basesoc_csr_bankarray_csrbank2_id1_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank2_id1_re <= basesoc_csr_bankarray_interface2_bank_bus_we;
basesoc_csr_bankarray_csrbank2_id1_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank2_id0_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank2_id0_re <= 1'd0;
basesoc_csr_bankarray_csrbank2_id0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank2_id0_re <= basesoc_csr_bankarray_interface2_bank_bus_we;
basesoc_csr_bankarray_csrbank2_id0_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank2_id1_w = dna_status[56:32];
assign basesoc_csr_bankarray_csrbank2_id0_w = dna_status[31:0];
assign dna_we = basesoc_csr_bankarray_csrbank2_id0_we;
assign basesoc_csr_bankarray_csrbank3_sel = (basesoc_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd6);
assign basesoc_csr_bankarray_csrbank3_out0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank3_out0_we <= 1'd0;
basesoc_csr_bankarray_csrbank3_out0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank3_sel & (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank3_out0_re <= basesoc_csr_bankarray_interface3_bank_bus_we;
basesoc_csr_bankarray_csrbank3_out0_we <= (~basesoc_csr_bankarray_interface3_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank3_out0_w = dshot_0_storage;
assign basesoc_csr_bankarray_csrbank4_sel = (basesoc_csr_bankarray_interface4_bank_bus_adr[13:9] == 3'd5);
assign basesoc_csr_bankarray_csrbank4_w0_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[2:0];
always @(*) begin
basesoc_csr_bankarray_csrbank4_w0_re <= 1'd0;
basesoc_csr_bankarray_csrbank4_w0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank4_w0_re <= basesoc_csr_bankarray_interface4_bank_bus_we;
basesoc_csr_bankarray_csrbank4_w0_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank4_r_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank4_r_re <= 1'd0;
basesoc_csr_bankarray_csrbank4_r_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank4_r_re <= basesoc_csr_bankarray_interface4_bank_bus_we;
basesoc_csr_bankarray_csrbank4_r_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we);
end
end
assign scl = _w_storage[0];
assign oe = _w_storage[1];
assign sda0 = _w_storage[2];
assign basesoc_csr_bankarray_csrbank4_w0_w = _w_storage[2:0];
assign _r_status = sda1;
assign basesoc_csr_bankarray_csrbank4_r_w = _r_status;
assign _r_we = basesoc_csr_bankarray_csrbank4_r_we;
assign basesoc_csr_bankarray_sel = (basesoc_csr_bankarray_sram_bus_adr[13:9] == 4'd8);
always @(*) begin
basesoc_csr_bankarray_sram_bus_dat_r <= 32'd0;
if (basesoc_csr_bankarray_sel_r) begin
basesoc_csr_bankarray_sram_bus_dat_r <= basesoc_csr_bankarray_dat_r;
end
end
assign basesoc_csr_bankarray_adr = basesoc_csr_bankarray_sram_bus_adr[4:0];
assign basesoc_csr_bankarray_csrbank5_sel = (basesoc_csr_bankarray_interface5_bank_bus_adr[13:9] == 2'd3);
assign basesoc_csr_bankarray_csrbank5_out0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank5_out0_re <= 1'd0;
basesoc_csr_bankarray_csrbank5_out0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank5_sel & (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank5_out0_re <= basesoc_csr_bankarray_interface5_bank_bus_we;
basesoc_csr_bankarray_csrbank5_out0_we <= (~basesoc_csr_bankarray_interface5_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank5_out0_w = leds_storage[1:0];
assign basesoc_csr_bankarray_csrbank6_sel = (basesoc_csr_bankarray_interface6_bank_bus_adr[13:9] == 4'd9);
assign basesoc_csr_bankarray_csrbank6_load0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_load0_re <= 1'd0;
basesoc_csr_bankarray_csrbank6_load0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank6_load0_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_load0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_reload0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_reload0_we <= 1'd0;
basesoc_csr_bankarray_csrbank6_reload0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank6_reload0_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_reload0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_en0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_en0_we <= 1'd0;
basesoc_csr_bankarray_csrbank6_en0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd2))) begin
basesoc_csr_bankarray_csrbank6_en0_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_en0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_update_value0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_update_value0_re <= 1'd0;
basesoc_csr_bankarray_csrbank6_update_value0_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd3))) begin
basesoc_csr_bankarray_csrbank6_update_value0_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_update_value0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_value_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_value_we <= 1'd0;
basesoc_csr_bankarray_csrbank6_value_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd4))) begin
basesoc_csr_bankarray_csrbank6_value_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_value_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_ev_status_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_ev_status_we <= 1'd0;
basesoc_csr_bankarray_csrbank6_ev_status_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd5))) begin
basesoc_csr_bankarray_csrbank6_ev_status_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_ev_status_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_ev_pending_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_ev_pending_re <= 1'd0;
basesoc_csr_bankarray_csrbank6_ev_pending_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd6))) begin
basesoc_csr_bankarray_csrbank6_ev_pending_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_ev_pending_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_ev_enable0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank6_ev_enable0_we <= 1'd0;
basesoc_csr_bankarray_csrbank6_ev_enable0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd7))) begin
basesoc_csr_bankarray_csrbank6_ev_enable0_re <= basesoc_csr_bankarray_interface6_bank_bus_we;
basesoc_csr_bankarray_csrbank6_ev_enable0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank6_load0_w = basesoc_timer_load_storage[31:0];
assign basesoc_csr_bankarray_csrbank6_reload0_w = basesoc_timer_reload_storage[31:0];
assign basesoc_csr_bankarray_csrbank6_en0_w = basesoc_timer_en_storage;
assign basesoc_csr_bankarray_csrbank6_update_value0_w = basesoc_timer_update_value_storage;
assign basesoc_csr_bankarray_csrbank6_value_w = basesoc_timer_value_status[31:0];
assign basesoc_timer_value_we = basesoc_csr_bankarray_csrbank6_value_we;
assign basesoc_timer_status_status = basesoc_timer_zero0;
assign basesoc_csr_bankarray_csrbank6_ev_status_w = basesoc_timer_status_status;
assign basesoc_timer_status_we = basesoc_csr_bankarray_csrbank6_ev_status_we;
assign basesoc_timer_pending_status = basesoc_timer_zero1;
assign basesoc_csr_bankarray_csrbank6_ev_pending_w = basesoc_timer_pending_status;
assign basesoc_timer_pending_we = basesoc_csr_bankarray_csrbank6_ev_pending_we;
assign basesoc_timer_zero2 = basesoc_timer_enable_storage;
assign basesoc_csr_bankarray_csrbank6_ev_enable0_w = basesoc_timer_enable_storage;
assign basesoc_csr_bankarray_csrbank7_sel = (basesoc_csr_bankarray_interface7_bank_bus_adr[13:9] == 4'd10);
assign basesoc_uart_rxtx_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[7:0];
always @(*) begin
basesoc_uart_rxtx_we <= 1'd0;
basesoc_uart_rxtx_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_uart_rxtx_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_uart_rxtx_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_txfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_txfull_we <= 1'd0;
basesoc_csr_bankarray_csrbank7_txfull_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank7_txfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_txfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_rxempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_rxempty_re <= 1'd0;
basesoc_csr_bankarray_csrbank7_rxempty_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd2))) begin
basesoc_csr_bankarray_csrbank7_rxempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_rxempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_ev_status_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_ev_status_re <= 1'd0;
basesoc_csr_bankarray_csrbank7_ev_status_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd3))) begin
basesoc_csr_bankarray_csrbank7_ev_status_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_ev_status_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_ev_pending_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_ev_pending_we <= 1'd0;
basesoc_csr_bankarray_csrbank7_ev_pending_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd4))) begin
basesoc_csr_bankarray_csrbank7_ev_pending_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_ev_pending_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_ev_enable0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_ev_enable0_we <= 1'd0;
basesoc_csr_bankarray_csrbank7_ev_enable0_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd5))) begin
basesoc_csr_bankarray_csrbank7_ev_enable0_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_ev_enable0_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_txempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_txempty_re <= 1'd0;
basesoc_csr_bankarray_csrbank7_txempty_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd6))) begin
basesoc_csr_bankarray_csrbank7_txempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_txempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_rxfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank7_rxfull_we <= 1'd0;
basesoc_csr_bankarray_csrbank7_rxfull_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd7))) begin
basesoc_csr_bankarray_csrbank7_rxfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we;
basesoc_csr_bankarray_csrbank7_rxfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank7_txfull_w = basesoc_uart_txfull_status;
assign basesoc_uart_txfull_we = basesoc_csr_bankarray_csrbank7_txfull_we;
assign basesoc_csr_bankarray_csrbank7_rxempty_w = basesoc_uart_rxempty_status;
assign basesoc_uart_rxempty_we = basesoc_csr_bankarray_csrbank7_rxempty_we;
always @(*) begin
basesoc_uart_status_status <= 2'd0;
basesoc_uart_status_status[0] <= basesoc_uart_tx0;
basesoc_uart_status_status[1] <= basesoc_uart_rx0;
end
assign basesoc_csr_bankarray_csrbank7_ev_status_w = basesoc_uart_status_status[1:0];
assign basesoc_uart_status_we = basesoc_csr_bankarray_csrbank7_ev_status_we;
always @(*) begin
basesoc_uart_pending_status <= 2'd0;
basesoc_uart_pending_status[0] <= basesoc_uart_tx1;
basesoc_uart_pending_status[1] <= basesoc_uart_rx1;
end
assign basesoc_csr_bankarray_csrbank7_ev_pending_w = basesoc_uart_pending_status[1:0];
assign basesoc_uart_pending_we = basesoc_csr_bankarray_csrbank7_ev_pending_we;
assign basesoc_uart_tx2 = basesoc_uart_enable_storage[0];
assign basesoc_uart_rx2 = basesoc_uart_enable_storage[1];
assign basesoc_csr_bankarray_csrbank7_ev_enable0_w = basesoc_uart_enable_storage[1:0];
assign basesoc_csr_bankarray_csrbank7_txempty_w = basesoc_uart_txempty_status;
assign basesoc_uart_txempty_we = basesoc_csr_bankarray_csrbank7_txempty_we;
assign basesoc_csr_bankarray_csrbank7_rxfull_w = basesoc_uart_rxfull_status;
assign basesoc_uart_rxfull_we = basesoc_csr_bankarray_csrbank7_rxfull_we;
assign basesoc_csr_bankarray_csrbank8_sel = (basesoc_csr_bankarray_interface8_bank_bus_adr[13:9] == 2'd2);
assign basesoc_csr_bankarray_csrbank8_temperature_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_temperature_we <= 1'd0;
basesoc_csr_bankarray_csrbank8_temperature_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd0))) begin
basesoc_csr_bankarray_csrbank8_temperature_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_temperature_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_vccint_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_vccint_we <= 1'd0;
basesoc_csr_bankarray_csrbank8_vccint_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd1))) begin
basesoc_csr_bankarray_csrbank8_vccint_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_vccint_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_vccaux_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_vccaux_re <= 1'd0;
basesoc_csr_bankarray_csrbank8_vccaux_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd2))) begin
basesoc_csr_bankarray_csrbank8_vccaux_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_vccaux_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_vccbram_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_vccbram_re <= 1'd0;
basesoc_csr_bankarray_csrbank8_vccbram_we <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd3))) begin
basesoc_csr_bankarray_csrbank8_vccbram_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_vccbram_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_eoc_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_eoc_we <= 1'd0;
basesoc_csr_bankarray_csrbank8_eoc_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd4))) begin
basesoc_csr_bankarray_csrbank8_eoc_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_eoc_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_eos_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0];
always @(*) begin
basesoc_csr_bankarray_csrbank8_eos_we <= 1'd0;
basesoc_csr_bankarray_csrbank8_eos_re <= 1'd0;
if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd5))) begin
basesoc_csr_bankarray_csrbank8_eos_re <= basesoc_csr_bankarray_interface8_bank_bus_we;
basesoc_csr_bankarray_csrbank8_eos_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we);
end
end
assign basesoc_csr_bankarray_csrbank8_temperature_w = xadc_temperature_status[11:0];
assign xadc_temperature_we = basesoc_csr_bankarray_csrbank8_temperature_we;
assign basesoc_csr_bankarray_csrbank8_vccint_w = xadc_vccint_status[11:0];
assign xadc_vccint_we = basesoc_csr_bankarray_csrbank8_vccint_we;
assign basesoc_csr_bankarray_csrbank8_vccaux_w = xadc_vccaux_status[11:0];
assign xadc_vccaux_we = basesoc_csr_bankarray_csrbank8_vccaux_we;
assign basesoc_csr_bankarray_csrbank8_vccbram_w = xadc_vccbram_status[11:0];
assign xadc_vccbram_we = basesoc_csr_bankarray_csrbank8_vccbram_we;
assign basesoc_csr_bankarray_csrbank8_eoc_w = xadc_eoc_status;
assign xadc_eoc_we = basesoc_csr_bankarray_csrbank8_eoc_we;
assign basesoc_csr_bankarray_csrbank8_eos_w = xadc_eos_status;
assign xadc_eos_we = basesoc_csr_bankarray_csrbank8_eos_we;
assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr;
assign basesoc_csr_interconnect_we = basesoc_basesoc_we;
assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w;
assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r;
assign basesoc_csr_bankarray_interface0_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface1_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface2_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface3_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface4_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface5_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface6_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface7_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface8_bank_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_sram_bus_adr = basesoc_csr_interconnect_adr;
assign basesoc_csr_bankarray_interface0_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface1_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface2_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface3_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface4_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface5_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface6_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface7_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface8_bank_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_sram_bus_we = basesoc_csr_interconnect_we;
assign basesoc_csr_bankarray_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface2_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface3_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface4_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface5_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface6_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface7_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_interface8_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_bankarray_sram_bus_dat_w = basesoc_csr_interconnect_dat_w;
assign basesoc_csr_interconnect_dat_r = (((((((((basesoc_csr_bankarray_interface0_bank_bus_dat_r | basesoc_csr_bankarray_interface1_bank_bus_dat_r) | basesoc_csr_bankarray_interface2_bank_bus_dat_r) | basesoc_csr_bankarray_interface3_bank_bus_dat_r) | basesoc_csr_bankarray_interface4_bank_bus_dat_r) | basesoc_csr_bankarray_interface5_bank_bus_dat_r) | basesoc_csr_bankarray_interface6_bank_bus_dat_r) | basesoc_csr_bankarray_interface7_bank_bus_dat_r) | basesoc_csr_bankarray_interface8_bank_bus_dat_r) | basesoc_csr_bankarray_sram_bus_dat_r);
always @(*) begin
array_muxed0 <= 30'd0;
case (basesoc_grant)
1'd0: begin
array_muxed0 <= basesoc_ibus_adr;
end
1'd1: begin
array_muxed0 <= basesoc_dbus_adr;
end
default: begin
array_muxed0 <= uart_1_wishbone_adr;
end
endcase
end
always @(*) begin
array_muxed1 <= 32'd0;
case (basesoc_grant)
1'd0: begin
array_muxed1 <= basesoc_ibus_dat_w;
end
1'd1: begin
array_muxed1 <= basesoc_dbus_dat_w;
end
default: begin
array_muxed1 <= uart_1_wishbone_dat_w;
end
endcase
end
always @(*) begin
array_muxed2 <= 4'd0;
case (basesoc_grant)
1'd0: begin
array_muxed2 <= basesoc_ibus_sel;
end
1'd1: begin
array_muxed2 <= basesoc_dbus_sel;
end
default: begin
array_muxed2 <= uart_1_wishbone_sel;
end
endcase
end
always @(*) begin
array_muxed3 <= 1'd0;
case (basesoc_grant)
1'd0: begin
array_muxed3 <= basesoc_ibus_cyc;
end
1'd1: begin
array_muxed3 <= basesoc_dbus_cyc;
end
default: begin
array_muxed3 <= uart_1_wishbone_cyc;
end
endcase
end
always @(*) begin
array_muxed4 <= 1'd0;
case (basesoc_grant)
1'd0: begin
array_muxed4 <= basesoc_ibus_stb;
end
1'd1: begin
array_muxed4 <= basesoc_dbus_stb;
end
default: begin
array_muxed4 <= uart_1_wishbone_stb;
end
endcase
end
always @(*) begin
array_muxed5 <= 1'd0;
case (basesoc_grant)
1'd0: begin
array_muxed5 <= basesoc_ibus_we;
end
1'd1: begin
array_muxed5 <= basesoc_dbus_we;
end
default: begin
array_muxed5 <= uart_1_wishbone_we;
end
endcase
end
always @(*) begin
array_muxed6 <= 3'd0;
case (basesoc_grant)
1'd0: begin
array_muxed6 <= basesoc_ibus_cti;
end
1'd1: begin
array_muxed6 <= basesoc_dbus_cti;
end
default: begin
array_muxed6 <= uart_1_wishbone_cti;
end
endcase
end
always @(*) begin
array_muxed7 <= 2'd0;
case (basesoc_grant)
1'd0: begin
array_muxed7 <= basesoc_ibus_bte;
end
1'd1: begin
array_muxed7 <= basesoc_dbus_bte;
end
default: begin
array_muxed7 <= uart_1_wishbone_bte;
end
endcase
end
assign basesoc_rx_rx = xilinxmultiregimpl0_regs1;
assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked);
assign buttons_status = xilinxmultiregimpl1_regs1;
assign xilinxmultiregimpl1 = {user_btn1, user_btn0};
assign uart_1_phy_rx_rx = xilinxmultiregimpl2_regs1;
//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------
always @(posedge idelay_clk) begin
if ((crg_reset_counter != 1'd0)) begin
crg_reset_counter <= (crg_reset_counter - 1'd1);
end else begin
crg_ic_reset <= 1'd0;
end
if (idelay_rst) begin
crg_reset_counter <= 4'd15;
crg_ic_reset <= 1'd1;
end
end
always @(posedge sys_clk) begin
if ((basesoc_bus_errors != 32'd4294967295)) begin
if (basesoc_bus_error) begin
basesoc_bus_errors <= (basesoc_bus_errors + 1'd1);
end
end
{basesoc_tx_tick, basesoc_tx_phase} <= 23'd4947802;
if (basesoc_tx_enable) begin
{basesoc_tx_tick, basesoc_tx_phase} <= (basesoc_tx_phase + 23'd4947802);
end
subfragments_rs232phytx0_state <= subfragments_rs232phytx0_next_state;
if (basesoc_tx_count_rs232phytx0_next_value_ce0) begin
basesoc_tx_count <= basesoc_tx_count_rs232phytx0_next_value0;
end
if (basesoc_serial_tx_rs232phytx0_next_value_ce1) begin
serial_tx <= basesoc_serial_tx_rs232phytx0_next_value1;
end
if (basesoc_tx_data_rs232phytx0_next_value_ce2) begin
basesoc_tx_data <= basesoc_tx_data_rs232phytx0_next_value2;
end
basesoc_rx_rx_d <= basesoc_rx_rx;
{basesoc_rx_tick, basesoc_rx_phase} <= 32'd2147483648;
if (basesoc_rx_enable) begin
{basesoc_rx_tick, basesoc_rx_phase} <= (basesoc_rx_phase + 23'd4947802);
end
subfragments_rs232phyrx0_state <= subfragments_rs232phyrx0_next_state;
if (basesoc_rx_count_rs232phyrx0_next_value_ce0) begin
basesoc_rx_count <= basesoc_rx_count_rs232phyrx0_next_value0;
end
if (basesoc_rx_data_rs232phyrx0_next_value_ce1) begin
basesoc_rx_data <= basesoc_rx_data_rs232phyrx0_next_value1;
end
if (basesoc_uart_tx_clear) begin
basesoc_uart_tx_pending <= 1'd0;
end
basesoc_uart_tx_trigger_d <= basesoc_uart_tx_trigger;
if ((basesoc_uart_tx_trigger & (~basesoc_uart_tx_trigger_d))) begin
basesoc_uart_tx_pending <= 1'd1;
end
if (basesoc_uart_rx_clear) begin
basesoc_uart_rx_pending <= 1'd0;
end
basesoc_uart_rx_trigger_d <= basesoc_uart_rx_trigger;
if ((basesoc_uart_rx_trigger & (~basesoc_uart_rx_trigger_d))) begin
basesoc_uart_rx_pending <= 1'd1;
end
if (basesoc_uart_tx_fifo_syncfifo_re) begin
basesoc_uart_tx_fifo_readable <= 1'd1;
end else begin
if (basesoc_uart_tx_fifo_re) begin
basesoc_uart_tx_fifo_readable <= 1'd0;
end
end
if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin
basesoc_uart_tx_fifo_produce <= (basesoc_uart_tx_fifo_produce + 1'd1);
end
if (basesoc_uart_tx_fifo_do_read) begin
basesoc_uart_tx_fifo_consume <= (basesoc_uart_tx_fifo_consume + 1'd1);
end
if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin
if ((~basesoc_uart_tx_fifo_do_read)) begin
basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (basesoc_uart_tx_fifo_do_read) begin
basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 - 1'd1);
end
end
if (basesoc_uart_rx_fifo_syncfifo_re) begin
basesoc_uart_rx_fifo_readable <= 1'd1;
end else begin
if (basesoc_uart_rx_fifo_re) begin
basesoc_uart_rx_fifo_readable <= 1'd0;
end
end
if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin
basesoc_uart_rx_fifo_produce <= (basesoc_uart_rx_fifo_produce + 1'd1);
end
if (basesoc_uart_rx_fifo_do_read) begin
basesoc_uart_rx_fifo_consume <= (basesoc_uart_rx_fifo_consume + 1'd1);
end
if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin
if ((~basesoc_uart_rx_fifo_do_read)) begin
basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (basesoc_uart_rx_fifo_do_read) begin
basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 - 1'd1);
end
end
if (basesoc_timer_en_storage) begin
if ((basesoc_timer_value == 1'd0)) begin
basesoc_timer_value <= basesoc_timer_reload_storage;
end else begin
basesoc_timer_value <= (basesoc_timer_value - 1'd1);
end
end else begin
basesoc_timer_value <= basesoc_timer_load_storage;
end
if (basesoc_timer_update_value_re) begin
basesoc_timer_value_status <= basesoc_timer_value;
end
if (basesoc_timer_zero_clear) begin
basesoc_timer_zero_pending <= 1'd0;
end
basesoc_timer_zero_trigger_d <= basesoc_timer_zero_trigger;
if ((basesoc_timer_zero_trigger & (~basesoc_timer_zero_trigger_d))) begin
basesoc_timer_zero_pending <= 1'd1;
end
if (directory0_re) begin
csrstorage0_storage <= directory0_r;
end
csrstorage0_re <= directory0_re;
if (csr_08000_re) begin
csrstorage1_storage <= csr_08000_r;
end
csrstorage1_re <= csr_08000_re;
basesoc_ram_bus_ack <= 1'd0;
if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin
basesoc_ram_bus_ack <= 1'd1;
end
if ((dna_count < 7'd114)) begin
dna_count <= (dna_count + 1'd1);
if (dna_clk) begin
dna_status <= {dna_status, dna_do};
end
end
if (xadc_drdy) begin
case (xadc_channel)
1'd0: begin
xadc_temperature_status <= (xadc_do >>> 3'd4);
end
1'd1: begin
xadc_vccint_status <= (xadc_do >>> 3'd4);
end
2'd2: begin
xadc_vccaux_status <= (xadc_do >>> 3'd4);
end
3'd6: begin
xadc_vccbram_status <= (xadc_do >>> 3'd4);
end
endcase
end
xadc_eoc_status <= ((xadc_eoc_status & (~xadc_eoc_we)) | xadc_eoc);
xadc_eos_status <= ((xadc_eos_status & (~xadc_eos_we)) | xadc_eos);
if (leds_done) begin
leds_chaser <= {leds_chaser, (~leds_chaser[1])};
end
if (leds_re) begin
leds_mode <= 1'd1;
end
if (leds_wait) begin
if ((~leds_done)) begin
leds_count <= (leds_count - 1'd1);
end
end else begin
leds_count <= 25'd25000000;
end
{uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= 23'd4947802;
if (uart_1_phy_tx_enable) begin
{uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= (uart_1_phy_tx_phase + 23'd4947802);
end
subfragments_rs232phytx1_state <= subfragments_rs232phytx1_next_state;
if (uart_1_phy_tx_count_rs232phytx1_next_value_ce0) begin
uart_1_phy_tx_count <= uart_1_phy_tx_count_rs232phytx1_next_value0;
end
if (tx_obj_rs232phytx1_next_value_ce1) begin
digital10 <= tx_obj_rs232phytx1_next_value1;
end
if (uart_1_phy_tx_data_rs232phytx1_next_value_ce2) begin
uart_1_phy_tx_data <= uart_1_phy_tx_data_rs232phytx1_next_value2;
end
uart_1_phy_rx_rx_d <= uart_1_phy_rx_rx;
{uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= 32'd2147483648;
if (uart_1_phy_rx_enable) begin
{uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= (uart_1_phy_rx_phase + 23'd4947802);
end
subfragments_rs232phyrx1_state <= subfragments_rs232phyrx1_next_state;
if (uart_1_phy_rx_count_rs232phyrx1_next_value_ce0) begin
uart_1_phy_rx_count <= uart_1_phy_rx_count_rs232phyrx1_next_value0;
end
if (uart_1_phy_rx_data_rs232phyrx1_next_value_ce1) begin
uart_1_phy_rx_data <= uart_1_phy_rx_data_rs232phyrx1_next_value1;
end
subfragments_state <= subfragments_next_state;
if (uart_1_bytes_count_next_value_ce0) begin
uart_1_bytes_count <= uart_1_bytes_count_next_value0;
end
if (uart_1_words_count_next_value_ce1) begin
uart_1_words_count <= uart_1_words_count_next_value1;
end
if (uart_1_cmd_next_value_ce2) begin
uart_1_cmd <= uart_1_cmd_next_value2;
end
if (uart_1_length_next_value_ce3) begin
uart_1_length <= uart_1_length_next_value3;
end
if (uart_1_address_next_value_ce4) begin
uart_1_address <= uart_1_address_next_value4;
end
if (uart_1_incr_next_value_ce5) begin
uart_1_incr <= uart_1_incr_next_value5;
end
if (uart_1_data_next_value_ce6) begin
uart_1_data <= uart_1_data_next_value6;
end
if (uart_1_reset) begin
uart_1_incr <= 1'd0;
subfragments_state <= 3'd0;
end
if (uart_1_wait) begin
if ((~uart_1_done)) begin
uart_1_count <= (uart_1_count - 1'd1);
end
end else begin
uart_1_count <= 24'd10000000;
end
basesoc_state <= basesoc_next_state;
case (basesoc_grant)
1'd0: begin
if ((~basesoc_request[0])) begin
if (basesoc_request[1]) begin
basesoc_grant <= 1'd1;
end else begin
if (basesoc_request[2]) begin
basesoc_grant <= 2'd2;
end
end
end
end
1'd1: begin
if ((~basesoc_request[1])) begin
if (basesoc_request[2]) begin
basesoc_grant <= 2'd2;
end else begin
if (basesoc_request[0]) begin
basesoc_grant <= 1'd0;
end
end
end
end
2'd2: begin
if ((~basesoc_request[2])) begin
if (basesoc_request[0]) begin
basesoc_grant <= 1'd0;
end else begin
if (basesoc_request[1]) begin
basesoc_grant <= 1'd1;
end
end
end
end
endcase
basesoc_slave_sel_r <= basesoc_slave_sel;
if (basesoc_wait) begin
if ((~basesoc_done)) begin
basesoc_count <= (basesoc_count - 1'd1);
end
end else begin
basesoc_count <= 20'd1000000;
end
basesoc_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank0_sel) begin
case (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_in_w;
end
endcase
end
buttons_re <= basesoc_csr_bankarray_csrbank0_in_re;
basesoc_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank1_sel) begin
case (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_reset0_w;
end
1'd1: begin
basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_scratch0_w;
end
2'd2: begin
basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_bus_errors_w;
end
endcase
end
if (basesoc_csr_bankarray_csrbank1_reset0_re) begin
basesoc_reset_storage[1:0] <= basesoc_csr_bankarray_csrbank1_reset0_r;
end
basesoc_reset_re <= basesoc_csr_bankarray_csrbank1_reset0_re;
if (basesoc_csr_bankarray_csrbank1_scratch0_re) begin
basesoc_scratch_storage[31:0] <= basesoc_csr_bankarray_csrbank1_scratch0_r;
end
basesoc_scratch_re <= basesoc_csr_bankarray_csrbank1_scratch0_re;
basesoc_bus_errors_re <= basesoc_csr_bankarray_csrbank1_bus_errors_re;
basesoc_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank2_sel) begin
case (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id1_w;
end
1'd1: begin
basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id0_w;
end
endcase
end
dna_re <= basesoc_csr_bankarray_csrbank2_id0_re;
basesoc_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank3_sel) begin
case (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_out0_w;
end
endcase
end
if (basesoc_csr_bankarray_csrbank3_out0_re) begin
dshot_0_storage <= basesoc_csr_bankarray_csrbank3_out0_r;
end
dshot_0_re <= basesoc_csr_bankarray_csrbank3_out0_re;
basesoc_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank4_sel) begin
case (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_w0_w;
end
1'd1: begin
basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_r_w;
end
endcase
end
if (basesoc_csr_bankarray_csrbank4_w0_re) begin
_w_storage[2:0] <= basesoc_csr_bankarray_csrbank4_w0_r;
end
_w_re <= basesoc_csr_bankarray_csrbank4_w0_re;
_r_re <= basesoc_csr_bankarray_csrbank4_r_re;
basesoc_csr_bankarray_sel_r <= basesoc_csr_bankarray_sel;
basesoc_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank5_sel) begin
case (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_out0_w;
end
endcase
end
if (basesoc_csr_bankarray_csrbank5_out0_re) begin
leds_storage[1:0] <= basesoc_csr_bankarray_csrbank5_out0_r;
end
leds_re <= basesoc_csr_bankarray_csrbank5_out0_re;
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank6_sel) begin
case (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_load0_w;
end
1'd1: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_reload0_w;
end
2'd2: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_en0_w;
end
2'd3: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_update_value0_w;
end
3'd4: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_value_w;
end
3'd5: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_status_w;
end
3'd6: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_pending_w;
end
3'd7: begin
basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_enable0_w;
end
endcase
end
if (basesoc_csr_bankarray_csrbank6_load0_re) begin
basesoc_timer_load_storage[31:0] <= basesoc_csr_bankarray_csrbank6_load0_r;
end
basesoc_timer_load_re <= basesoc_csr_bankarray_csrbank6_load0_re;
if (basesoc_csr_bankarray_csrbank6_reload0_re) begin
basesoc_timer_reload_storage[31:0] <= basesoc_csr_bankarray_csrbank6_reload0_r;
end
basesoc_timer_reload_re <= basesoc_csr_bankarray_csrbank6_reload0_re;
if (basesoc_csr_bankarray_csrbank6_en0_re) begin
basesoc_timer_en_storage <= basesoc_csr_bankarray_csrbank6_en0_r;
end
basesoc_timer_en_re <= basesoc_csr_bankarray_csrbank6_en0_re;
if (basesoc_csr_bankarray_csrbank6_update_value0_re) begin
basesoc_timer_update_value_storage <= basesoc_csr_bankarray_csrbank6_update_value0_r;
end
basesoc_timer_update_value_re <= basesoc_csr_bankarray_csrbank6_update_value0_re;
basesoc_timer_value_re <= basesoc_csr_bankarray_csrbank6_value_re;
basesoc_timer_status_re <= basesoc_csr_bankarray_csrbank6_ev_status_re;
if (basesoc_csr_bankarray_csrbank6_ev_pending_re) begin
basesoc_timer_pending_r <= basesoc_csr_bankarray_csrbank6_ev_pending_r;
end
basesoc_timer_pending_re <= basesoc_csr_bankarray_csrbank6_ev_pending_re;
if (basesoc_csr_bankarray_csrbank6_ev_enable0_re) begin
basesoc_timer_enable_storage <= basesoc_csr_bankarray_csrbank6_ev_enable0_r;
end
basesoc_timer_enable_re <= basesoc_csr_bankarray_csrbank6_ev_enable0_re;
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank7_sel) begin
case (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_uart_rxtx_w;
end
1'd1: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txfull_w;
end
2'd2: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxempty_w;
end
2'd3: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_status_w;
end
3'd4: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_pending_w;
end
3'd5: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_enable0_w;
end
3'd6: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txempty_w;
end
3'd7: begin
basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxfull_w;
end
endcase
end
basesoc_uart_txfull_re <= basesoc_csr_bankarray_csrbank7_txfull_re;
basesoc_uart_rxempty_re <= basesoc_csr_bankarray_csrbank7_rxempty_re;
basesoc_uart_status_re <= basesoc_csr_bankarray_csrbank7_ev_status_re;
if (basesoc_csr_bankarray_csrbank7_ev_pending_re) begin
basesoc_uart_pending_r[1:0] <= basesoc_csr_bankarray_csrbank7_ev_pending_r;
end
basesoc_uart_pending_re <= basesoc_csr_bankarray_csrbank7_ev_pending_re;
if (basesoc_csr_bankarray_csrbank7_ev_enable0_re) begin
basesoc_uart_enable_storage[1:0] <= basesoc_csr_bankarray_csrbank7_ev_enable0_r;
end
basesoc_uart_enable_re <= basesoc_csr_bankarray_csrbank7_ev_enable0_re;
basesoc_uart_txempty_re <= basesoc_csr_bankarray_csrbank7_txempty_re;
basesoc_uart_rxfull_re <= basesoc_csr_bankarray_csrbank7_rxfull_re;
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= 1'd0;
if (basesoc_csr_bankarray_csrbank8_sel) begin
case (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0])
1'd0: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_temperature_w;
end
1'd1: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccint_w;
end
2'd2: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccaux_w;
end
2'd3: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccbram_w;
end
3'd4: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eoc_w;
end
3'd5: begin
basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eos_w;
end
endcase
end
xadc_temperature_re <= basesoc_csr_bankarray_csrbank8_temperature_re;
xadc_vccint_re <= basesoc_csr_bankarray_csrbank8_vccint_re;
xadc_vccaux_re <= basesoc_csr_bankarray_csrbank8_vccaux_re;
xadc_vccbram_re <= basesoc_csr_bankarray_csrbank8_vccbram_re;
xadc_eoc_re <= basesoc_csr_bankarray_csrbank8_eoc_re;
xadc_eos_re <= basesoc_csr_bankarray_csrbank8_eos_re;
if (sys_rst) begin
basesoc_reset_storage <= 2'd0;
basesoc_reset_re <= 1'd0;
basesoc_scratch_storage <= 32'd305419896;
basesoc_scratch_re <= 1'd0;
basesoc_bus_errors_re <= 1'd0;
basesoc_bus_errors <= 32'd0;
serial_tx <= 1'd1;
basesoc_tx_tick <= 1'd0;
basesoc_rx_tick <= 1'd0;
basesoc_rx_rx_d <= 1'd0;
basesoc_uart_txfull_re <= 1'd0;
basesoc_uart_rxempty_re <= 1'd0;
basesoc_uart_tx_pending <= 1'd0;
basesoc_uart_tx_trigger_d <= 1'd0;
basesoc_uart_rx_pending <= 1'd0;
basesoc_uart_rx_trigger_d <= 1'd0;
basesoc_uart_status_re <= 1'd0;
basesoc_uart_pending_re <= 1'd0;
basesoc_uart_pending_r <= 2'd0;
basesoc_uart_enable_storage <= 2'd0;
basesoc_uart_enable_re <= 1'd0;
basesoc_uart_txempty_re <= 1'd0;
basesoc_uart_rxfull_re <= 1'd0;
basesoc_uart_tx_fifo_readable <= 1'd0;
basesoc_uart_tx_fifo_level0 <= 5'd0;
basesoc_uart_tx_fifo_produce <= 4'd0;
basesoc_uart_tx_fifo_consume <= 4'd0;
basesoc_uart_rx_fifo_readable <= 1'd0;
basesoc_uart_rx_fifo_level0 <= 5'd0;
basesoc_uart_rx_fifo_produce <= 4'd0;
basesoc_uart_rx_fifo_consume <= 4'd0;
basesoc_timer_load_storage <= 32'd0;
basesoc_timer_load_re <= 1'd0;
basesoc_timer_reload_storage <= 32'd0;
basesoc_timer_reload_re <= 1'd0;
basesoc_timer_en_storage <= 1'd0;
basesoc_timer_en_re <= 1'd0;
basesoc_timer_update_value_storage <= 1'd0;
basesoc_timer_update_value_re <= 1'd0;
basesoc_timer_value_status <= 32'd0;
basesoc_timer_value_re <= 1'd0;
basesoc_timer_zero_pending <= 1'd0;
basesoc_timer_zero_trigger_d <= 1'd0;
basesoc_timer_status_re <= 1'd0;
basesoc_timer_pending_re <= 1'd0;
basesoc_timer_pending_r <= 1'd0;
basesoc_timer_enable_storage <= 1'd0;
basesoc_timer_enable_re <= 1'd0;
basesoc_timer_value <= 32'd0;
csrstorage0_storage <= 1'd140989193;
csrstorage0_re <= 1'd0;
csrstorage1_storage <= 1'd0;
csrstorage1_re <= 1'd0;
basesoc_ram_bus_ack <= 1'd0;
dna_status <= 57'd0;
dna_re <= 1'd0;
dna_count <= 7'd0;
xadc_temperature_status <= 12'd0;
xadc_temperature_re <= 1'd0;
xadc_vccint_status <= 12'd0;
xadc_vccint_re <= 1'd0;
xadc_vccaux_status <= 12'd0;
xadc_vccaux_re <= 1'd0;
xadc_vccbram_status <= 12'd0;
xadc_vccbram_re <= 1'd0;
xadc_eoc_status <= 1'd0;
xadc_eoc_re <= 1'd0;
xadc_eos_status <= 1'd0;
xadc_eos_re <= 1'd0;
leds_storage <= 2'd0;
leds_re <= 1'd0;
leds_chaser <= 2'd0;
leds_mode <= 1'd0;
leds_count <= 25'd25000000;
buttons_re <= 1'd0;
_w_storage <= 3'd0;
_w_re <= 1'd0;
_r_re <= 1'd0;
digital10 <= 1'd1;
uart_1_phy_tx_tick <= 1'd0;
uart_1_phy_rx_tick <= 1'd0;
uart_1_phy_rx_rx_d <= 1'd0;
uart_1_incr <= 1'd0;
uart_1_count <= 24'd10000000;
dshot_0_storage <= 1'd0;
dshot_0_re <= 1'd0;
subfragments_rs232phytx0_state <= 1'd0;
subfragments_rs232phyrx0_state <= 1'd0;
subfragments_rs232phytx1_state <= 1'd0;
subfragments_rs232phyrx1_state <= 1'd0;
subfragments_state <= 3'd0;
basesoc_grant <= 2'd0;
basesoc_slave_sel_r <= 3'd0;
basesoc_count <= 20'd1000000;
basesoc_csr_bankarray_sel_r <= 1'd0;
basesoc_state <= 1'd0;
end
xilinxmultiregimpl0_regs0 <= serial_rx;
xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0};
xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
xilinxmultiregimpl2_regs0 <= digital11;
xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0;
end
//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Memory mem: 24-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem[0:23];
initial begin
$readmemh("mem.init", mem);
end
reg [4:0] mem_adr0;
always @(posedge sys_clk) begin
mem_adr0 <= basesoc_csr_bankarray_adr;
end
assign basesoc_csr_bankarray_dat_r = mem[mem_adr0];
//------------------------------------------------------------------------------
// Memory storage: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_clk) begin
if (basesoc_uart_tx_fifo_wrport_we)
storage[basesoc_uart_tx_fifo_wrport_adr] <= basesoc_uart_tx_fifo_wrport_dat_w;
storage_dat0 <= storage[basesoc_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (basesoc_uart_tx_fifo_rdport_re)
storage_dat1 <= storage[basesoc_uart_tx_fifo_rdport_adr];
end
assign basesoc_uart_tx_fifo_wrport_dat_r = storage_dat0;
assign basesoc_uart_tx_fifo_rdport_dat_r = storage_dat1;
//------------------------------------------------------------------------------
// Memory storage_1: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_1[0:15];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge sys_clk) begin
if (basesoc_uart_rx_fifo_wrport_we)
storage_1[basesoc_uart_rx_fifo_wrport_adr] <= basesoc_uart_rx_fifo_wrport_dat_w;
storage_1_dat0 <= storage_1[basesoc_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (basesoc_uart_rx_fifo_rdport_re)
storage_1_dat1 <= storage_1[basesoc_uart_rx_fifo_rdport_adr];
end
assign basesoc_uart_rx_fifo_wrport_dat_r = storage_1_dat0;
assign basesoc_uart_rx_fifo_rdport_dat_r = storage_1_dat1;
BUFG BUFG(
.I(crg_clkout0),
.O(crg_clkout_buf0)
);
BUFG BUFG_1(
.I(crg_clkout1),
.O(crg_clkout_buf1)
);
BUFG BUFG_2(
.I(crg_clkout2),
.O(crg_clkout_buf2)
);
IDELAYCTRL IDELAYCTRL(
.REFCLK(idelay_clk),
.RST(crg_ic_reset)
);
//------------------------------------------------------------------------------
// Memory mem_1: 16384-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: ---- |
reg [31:0] mem_1[0:16383];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [31:0] mem_1_dat0;
always @(posedge sys_clk) begin
mem_1_dat0 <= mem_1[basesoc_adr];
end
assign basesoc_dat_r = mem_1_dat0;
issiram issiram(
.clk(sys_clk),
.rst(sys_rst),
.wbs_adr_i(sram_bus_adr),
.wbs_cyc_i(sram_bus_cyc),
.wbs_dat_i(sram_bus_dat_w),
.wbs_sel_i(sram_bus_sel),
.wbs_stb_i(sram_bus_stb),
.wbs_we_i(sram_bus_we),
.mem_dat(issiram_data),
.mem_adr(issiram_addr),
.mem_ce_n(issiram_cen),
.mem_oe_n(issiram_oen),
.mem_we_n(issiram_wen),
.wbs_ack_o(sram_bus_ack),
.wbs_dat_o(sram_bus_dat_r)
);
DNA_PORT DNA_PORT(
.CLK(dna_clk),
.DIN(dna_status[56]),
.READ((dna_count < 2'd2)),
.SHIFT(1'd1),
.DOUT(dna_do)
);
XADC #(
.INIT_40(16'd36864),
.INIT_41(14'd12016),
.INIT_42(11'd1024),
.INIT_48(15'd18177),
.INIT_49(4'd15),
.INIT_4A(15'd18176),
.INIT_4B(1'd0),
.INIT_4C(1'd0),
.INIT_4D(1'd0),
.INIT_4E(1'd0),
.INIT_4F(1'd0),
.INIT_50(16'd46573),
.INIT_51(15'd22937),
.INIT_52(16'd41287),
.INIT_53(16'd56797),
.INIT_54(16'd43322),
.INIT_55(15'd20753),
.INIT_56(16'd37355),
.INIT_57(16'd44622),
.INIT_58(15'd22937),
.INIT_5C(15'd20753)
) XADC (
.CONVST(1'd0),
.CONVSTCLK(1'd0),
.DADDR(xadc_dadr),
.DCLK(sys_clk),
.DEN(xadc_den),
.DI(xadc_di),
.DWE(xadc_dwe),
.RESET(sys_rst),
.VAUXN(1'd0),
.VAUXP(1'd0),
.VN(1'd0),
.VP(1'd0),
.ALM(xadc_alarm),
.BUSY(xadc_busy),
.CHANNEL(xadc_channel),
.DO(xadc_do),
.DRDY(xadc_drdy),
.EOC(xadc_eoc),
.EOS(xadc_eos),
.OT(xadc_ot)
);
assign pmod0 = (~scl) ? 1'd0 : 1'bz;
assign pmod1 = (oe & (~sda0)) ? 1'd0 : 1'bz;
assign sda1 = pmod1;
A2P_WB A2P_WB(
.clk(sys_clk),
.dBusWB_ACK(basesoc_dbus_ack),
.dBusWB_DAT_MISO(basesoc_dbus_dat_r),
.dBusWB_ERR(basesoc_dbus_err),
.externalInterrupt(basesoc_interrupt[0]),
.externalInterruptS(basesoc_interruptS),
.externalResetVector(basesoc_a2p),
.iBusWB_ACK(basesoc_ibus_ack),
.iBusWB_DAT_MISO(basesoc_ibus_dat_r),
.iBusWB_ERR(basesoc_ibus_err),
.reset((sys_rst | basesoc_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(1'd0),
.dBusWB_ADR(basesoc_dbus_adr),
.dBusWB_BTE(basesoc_dbus_bte),
.dBusWB_CTI(basesoc_dbus_cti),
.dBusWB_CYC(basesoc_dbus_cyc),
.dBusWB_DAT_MOSI(basesoc_dbus_dat_w),
.dBusWB_SEL(basesoc_dbus_sel),
.dBusWB_STB(basesoc_dbus_stb),
.dBusWB_WE(basesoc_dbus_we),
.iBusWB_ADR(basesoc_ibus_adr),
.iBusWB_BTE(basesoc_ibus_bte),
.iBusWB_CTI(basesoc_ibus_cti),
.iBusWB_CYC(basesoc_ibus_cyc),
.iBusWB_DAT_MOSI(basesoc_ibus_dat_w),
.iBusWB_SEL(basesoc_ibus_sel),
.iBusWB_STB(basesoc_ibus_stb),
.iBusWB_WE(basesoc_ibus_we)
);
FD FD(
.C(crg_clkin),
.D(crg_reset),
.Q(subfragments_reset0)
);
FD FD_1(
.C(crg_clkin),
.D(subfragments_reset0),
.Q(subfragments_reset1)
);
FD FD_2(
.C(crg_clkin),
.D(subfragments_reset1),
.Q(subfragments_reset2)
);
FD FD_3(
.C(crg_clkin),
.D(subfragments_reset2),
.Q(subfragments_reset3)
);
FD FD_4(
.C(crg_clkin),
.D(subfragments_reset3),
.Q(subfragments_reset4)
);
FD FD_5(
.C(crg_clkin),
.D(subfragments_reset4),
.Q(subfragments_reset5)
);
FD FD_6(
.C(crg_clkin),
.D(subfragments_reset5),
.Q(subfragments_reset6)
);
FD FD_7(
.C(crg_clkin),
.D(subfragments_reset6),
.Q(subfragments_reset7)
);
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(6'd50),
.CLKIN1_PERIOD(83.33333333333333),
.CLKOUT0_DIVIDE_F(3'd6),
.CLKOUT0_PHASE(1'd0),
.CLKOUT1_DIVIDE(2'd3),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(2'd3),
.CLKOUT2_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01)
) MMCME2_ADV (
.CLKFBIN(subfragments_mmcm_fb),
.CLKIN1(crg_clkin),
.PWRDWN(crg_power_down),
.RST(subfragments_reset7),
.CLKFBOUT(subfragments_mmcm_fb),
.CLKOUT0(crg_clkout0),
.CLKOUT1(crg_clkout1),
.CLKOUT2(crg_clkout2),
.LOCKED(crg_locked)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
.C(sys_clk),
.CE(1'd1),
.D(1'd0),
.PRE(xilinxasyncresetsynchronizerimpl0),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(sys_clk),
.CE(1'd1),
.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
.PRE(xilinxasyncresetsynchronizerimpl0),
.Q(sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys2x_clk),
.CE(1'd1),
.D(1'd0),
.PRE(xilinxasyncresetsynchronizerimpl1),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys2x_clk),
.CE(1'd1),
.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
.PRE(xilinxasyncresetsynchronizerimpl1),
.Q(xilinxasyncresetsynchronizerimpl1_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(idelay_clk),
.CE(1'd1),
.D(1'd0),
.PRE(xilinxasyncresetsynchronizerimpl2),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(idelay_clk),
.CE(1'd1),
.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
.PRE(xilinxasyncresetsynchronizerimpl2),
.Q(idelay_rst)
);
endmodule
// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2021-11-11 08:18:47.
//------------------------------------------------------------------------------