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wtf 1 year ago
parent
commit
098efd77c6
  1. 3
      build/openroad/.gitignore
  2. 0
      build/openroad/allrams_100.log
  3. 2436
      build/openroad/allrams_40.log
  4. 13
      build/openroad/config.mk
  5. 7
      build/openroad/constraint.sdc
  6. BIN
      build/openroad/imaynotbea10buttheboyssayicleanupgood.png
  7. 80184
      build/openroad/logs/clk_25_allrams/1_1_yosys.log
  8. 2
      build/openroad/logs/clk_25_allrams/2_1_floorplan.json
  9. 320
      build/openroad/logs/clk_25_allrams/2_1_floorplan.log
  10. 2
      build/openroad/logs/clk_25_allrams/2_2_floorplan_io.json
  11. 27
      build/openroad/logs/clk_25_allrams/2_2_floorplan_io.log
  12. 2
      build/openroad/logs/clk_25_allrams/2_3_tdms.json
  13. 25
      build/openroad/logs/clk_25_allrams/2_3_tdms_place.log
  14. 2
      build/openroad/logs/clk_25_allrams/2_4_mplace.json
  15. 25
      build/openroad/logs/clk_25_allrams/2_4_mplace.log
  16. 2
      build/openroad/logs/clk_25_allrams/2_5_tapcell.json
  17. 28
      build/openroad/logs/clk_25_allrams/2_5_tapcell.log
  18. 2
      build/openroad/logs/clk_25_allrams/2_6_pdn.json
  19. 47
      build/openroad/logs/clk_25_allrams/2_6_pdn.log
  20. 2
      build/openroad/logs/clk_25_allrams/3_1_place_gp.json
  21. 484
      build/openroad/logs/clk_25_allrams/3_1_place_gp.log
  22. 2
      build/openroad/logs/clk_25_allrams/3_2_place_iop.json
  23. 39
      build/openroad/logs/clk_25_allrams/3_2_place_iop.log
  24. 2
      build/openroad/logs/clk_25_allrams/3_3_resizer.json
  25. 76221
      build/openroad/logs/clk_25_allrams/3_3_resizer.log
  26. 2
      build/openroad/logs/clk_25_allrams/3_4_opendp.json
  27. 76191
      build/openroad/logs/clk_25_allrams/3_4_opendp.log
  28. 2
      build/openroad/logs/clk_25_allrams/4_1_cts.json
  29. 308914
      build/openroad/logs/clk_25_allrams/4_1_cts.log
  30. 2
      build/openroad/logs/clk_25_allrams/4_2_cts_fillcell.json
  31. 29
      build/openroad/logs/clk_25_allrams/4_2_cts_fillcell.log
  32. 2
      build/openroad/logs/clk_25_allrams/5_1_fastroute.json
  33. 78897
      build/openroad/logs/clk_25_allrams/5_1_fastroute.log
  34. 4
      build/openroad/logs/clk_25_allrams/5_2_TritonRoute.json
  35. 1481
      build/openroad/logs/clk_25_allrams/5_2_TritonRoute.log
  36. 42
      build/openroad/logs/clk_25_allrams/6_1_merge.log
  37. 2
      build/openroad/logs/clk_25_allrams/6_report.json
  38. 78509
      build/openroad/logs/clk_25_allrams/6_report.log
  39. 80184
      build/openroad/logs/clk_40_allrams/1_1_yosys.log
  40. 2
      build/openroad/logs/clk_40_allrams/2_1_floorplan.json
  41. 320
      build/openroad/logs/clk_40_allrams/2_1_floorplan.log
  42. 2
      build/openroad/logs/clk_40_allrams/2_2_floorplan_io.json
  43. 27
      build/openroad/logs/clk_40_allrams/2_2_floorplan_io.log
  44. 2
      build/openroad/logs/clk_40_allrams/2_3_tdms.json
  45. 25
      build/openroad/logs/clk_40_allrams/2_3_tdms_place.log
  46. 2
      build/openroad/logs/clk_40_allrams/2_4_mplace.json
  47. 25
      build/openroad/logs/clk_40_allrams/2_4_mplace.log
  48. 2
      build/openroad/logs/clk_40_allrams/2_5_tapcell.json
  49. 28
      build/openroad/logs/clk_40_allrams/2_5_tapcell.log
  50. 2
      build/openroad/logs/clk_40_allrams/2_6_pdn.json
  51. 47
      build/openroad/logs/clk_40_allrams/2_6_pdn.log
  52. 2
      build/openroad/logs/clk_40_allrams/3_1_place_gp.json
  53. 484
      build/openroad/logs/clk_40_allrams/3_1_place_gp.log
  54. 2
      build/openroad/logs/clk_40_allrams/3_2_place_iop.json
  55. 39
      build/openroad/logs/clk_40_allrams/3_2_place_iop.log
  56. 2
      build/openroad/logs/clk_40_allrams/3_3_resizer.json
  57. 76729
      build/openroad/logs/clk_40_allrams/3_3_resizer.log
  58. 2
      build/openroad/logs/clk_40_allrams/3_4_opendp.json
  59. 76699
      build/openroad/logs/clk_40_allrams/3_4_opendp.log
  60. 2
      build/openroad/logs/clk_40_allrams/4_1_cts.json
  61. 308904
      build/openroad/logs/clk_40_allrams/4_1_cts.log
  62. 2
      build/openroad/logs/clk_40_allrams/4_2_cts_fillcell.json
  63. 29
      build/openroad/logs/clk_40_allrams/4_2_cts_fillcell.log
  64. 2
      build/openroad/logs/clk_40_allrams/5_1_fastroute.json
  65. 78809
      build/openroad/logs/clk_40_allrams/5_1_fastroute.log
  66. 4
      build/openroad/logs/clk_40_allrams/5_2_TritonRoute.json
  67. 1437
      build/openroad/logs/clk_40_allrams/5_2_TritonRoute.log
  68. 42
      build/openroad/logs/clk_40_allrams/6_1_merge.log
  69. 2
      build/openroad/logs/clk_40_allrams/6_report.json
  70. 78599
      build/openroad/logs/clk_40_allrams/6_report.log
  71. 39
      build/openroad/readme.md

3
build/openroad/.gitignore vendored

@ -1 +1,2 @@ @@ -1 +1,2 @@
dffram/
dffram/
output/

0
build/openroad/allrams.log → build/openroad/allrams_100.log

2436
build/openroad/allrams_40.log

File diff suppressed because it is too large Load Diff

13
build/openroad/config.mk

@ -3,8 +3,8 @@ export DESIGN_NICKNAME = a2p @@ -3,8 +3,8 @@ export DESIGN_NICKNAME = a2p
export DESIGN_NAME = A2P_WB
export PLATFORM = sky130hd

export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES := $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
export SDC_FILE := ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

$(info Source files:)
$(info $(VERILOG_FILES))
@ -25,11 +25,18 @@ export SYNTH_MAX_TRAN ?= 100 @@ -25,11 +25,18 @@ export SYNTH_MAX_TRAN ?= 100

export REPORT_SLACK_MAX_PATHS ?= 100

#HACK! uniquify logs, objects, reports, results
export DESIGN_NICKNAME := $(DESIGN_NICKNAME)/output/$(shell date "+%Y%m%d%H%M%S")
$(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
# except there's a bug (yosys?)


# ----------------------------------------------------------------------------------
# ----------------------------------------------------------------------------------
# CTS

# forget about this for now - occurred when added dffram dir/caches. anton says hold misses are fake anyway :)
# (at least at 100mhz)
# do i need something else from dffram build?
# Repair hold violations...
# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
@ -37,4 +44,4 @@ export REPORT_SLACK_MAX_PATHS ?= 100 @@ -37,4 +44,4 @@ export REPORT_SLACK_MAX_PATHS ?= 100
# [INFO RSZ-0032] Inserted 213923 hold buffers.
# [ERROR DPL-0019] detailed placement failed on hold33177
# continue if cts wants to barf...
export WTF_CTS_IGNORE_HOLD_MISSES = 1
#export WTF_CTS_IGNORE_HOLD_MISSES = 1

7
build/openroad/constraint.sdc

@ -5,7 +5,10 @@ @@ -5,7 +5,10 @@

set clk_name clk
# set clk_period 50.0 ;# make it easy for or
set clk_period 10.0
#set clk_period 10.0 ;# 100Mhz
#set clk_period 25.0 ;# 40Mhz
set clk_period 40.0 ;# 25Mhz

puts "\[WTF\] clk_period=$clk_period"

set clkPort [get_ports $clk_name]
@ -26,4 +29,4 @@ set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs] @@ -26,4 +29,4 @@ set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]
# false paths

set_false_path -from [get_ports {reset}] -to [get_clocks clk]

set_false_path -from [get_ports {externalResetVector}] -to [get_clocks clk]

BIN
build/openroad/imaynotbea10buttheboyssayicleanupgood.png

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80184
build/openroad/logs/clk_25_allrams/1_1_yosys.log

File diff suppressed because it is too large Load Diff

2
build/openroad/logs/clk_25_allrams/2_1_floorplan.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

320
build/openroad/logs/clk_25_allrams/2_1_floorplan.log

@ -0,0 +1,320 @@ @@ -0,0 +1,320 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[WTF] clk_period=40.0
number instances in verilog is 432348
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 34250 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um

==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 v _346224_/B (sky130_fd_sc_hd__nand2_1)
0.05 0.05 0.05 ^ _346224_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.05 0.01 0.06 ^ _404211_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.06 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.11 0.11 library removal time
0.11 data required time
-----------------------------------------------------------------------------
0.11 data required time
-0.06 data arrival time
-----------------------------------------------------------------------------
-0.05 slack (VIOLATED)


Startpoint: iBusWB_DAT_MISO[0] (input port clocked by clk)
Endpoint: _348143_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[0] (in)
1 0.00 iBusWB_DAT_MISO[0] (net)
0.00 0.00 0.00 ^ _348143_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _348143_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 39.93 library recovery time
39.93 data required time
-----------------------------------------------------------------------------
39.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
39.85 slack (MET)


Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
7 0.02 _057091_ (net)
0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _057181_ (net)
0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 0.92 _057233_ (net)
26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.10 _057237_ (net)
8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.00 _057243_ (net)
0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 33.23 _057333_ (net)
955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6504.75 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 19.81 library setup time
19.81 data required time
-----------------------------------------------------------------------------
19.81 data required time
-6504.75 data arrival time
-----------------------------------------------------------------------------
-6484.94 slack (VIOLATED)



==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 39.93 library recovery time
39.93 data required time
-----------------------------------------------------------------------------
39.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
39.85 slack (MET)


Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
7 0.02 _057091_ (net)
0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _057181_ (net)
0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 0.92 _057233_ (net)
26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.10 _057237_ (net)
8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.00 _057243_ (net)
0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 33.23 _057333_ (net)
955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6504.75 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 19.81 library setup time
19.81 data required time
-----------------------------------------------------------------------------
19.81 data required time
-6504.75 data arrival time
-----------------------------------------------------------------------------
-6484.94 slack (VIOLATED)



==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -13826056.00

==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -6484.94

==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -6484.94

==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[0]/CLK ^
0.00 0.00 0.26


==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.00e-01 2.91e-03 9.29e-07 1.03e-01 22.0%
Combinational 3.45e-01 2.11e-02 8.90e-07 3.66e-01 78.1%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 4.45e-01 2.40e-02 1.82e-06 4.69e-01 100.0%
94.9% 5.1% 0.0%

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 4627248 u^2 23% utilization.

Elapsed time: 2:28.41[h:]min:sec. CPU time: user 147.85 sys 0.52 (99%). Peak memory: 1319716KB.

2
build/openroad/logs/clk_25_allrams/2_2_floorplan_io.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

27
build/openroad/logs/clk_25_allrams/2_2_floorplan_io.log

@ -0,0 +1,27 @@ @@ -0,0 +1,27 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
Elapsed time: 0:05.59[h:]min:sec. CPU time: user 5.30 sys 0.26 (99%). Peak memory: 591184KB.

2
build/openroad/logs/clk_25_allrams/2_3_tdms.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

25
build/openroad/logs/clk_25_allrams/2_3_tdms_place.log

@ -0,0 +1,25 @@ @@ -0,0 +1,25 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[WTF] clk_period=40.0
No macros found: Skipping global_placement
Elapsed time: 0:05.66[h:]min:sec. CPU time: user 5.27 sys 0.36 (99%). Peak memory: 575116KB.

2
build/openroad/logs/clk_25_allrams/2_4_mplace.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

25
build/openroad/logs/clk_25_allrams/2_4_mplace.log

@ -0,0 +1,25 @@ @@ -0,0 +1,25 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
[WTF] clk_period=40.0
No macros found: Skipping macro_placement
Elapsed time: 0:05.68[h:]min:sec. CPU time: user 5.45 sys 0.20 (99%). Peak memory: 575012KB.

2
build/openroad/logs/clk_25_allrams/2_5_tapcell.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

28
build/openroad/logs/clk_25_allrams/2_5_tapcell.log

@ -0,0 +1,28 @@ @@ -0,0 +1,28 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[WARNING TAP-0014] endcap_cpp option is deprecated.
[INFO TAP-0001] Found 0 macro blocks.
[INFO TAP-0002] Original rows: 1535
[INFO TAP-0003] Created 0 rows for a total of 1535 rows.
[INFO TAP-0005] Inserted 265901 tapcells.
Elapsed time: 0:05.89[h:]min:sec. CPU time: user 5.69 sys 0.17 (99%). Peak memory: 427276KB.

2
build/openroad/logs/clk_25_allrams/2_6_pdn.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

47
build/openroad/logs/clk_25_allrams/2_6_pdn.log

@ -0,0 +1,47 @@ @@ -0,0 +1,47 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
config: ./platforms/sky130hd/pdn.cfg
[INFO PDN-0008] Design name is A2P_WB.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 5.440 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 27.140 offset: 13.570
Layer: met5 - width: 1.600 pitch: 27.200 offset: 13.600
Connect: {met1 met4} {met4 met5}
Type: macro, CORE_macro_grid_1
Macro orientation: R0 R180 MX MY
Connect: {met4_PIN_ver met5}
Type: macro, CORE_macro_grid_2
Macro orientation: R90 R270 MXR90 MYR90
Connect: {met4_PIN_hor met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - grid.
[INFO PDN-0015] Writing to database.
Elapsed time: 0:45.36[h:]min:sec. CPU time: user 44.04 sys 1.27 (99%). Peak memory: 3756272KB.

2
build/openroad/logs/clk_25_allrams/3_1_place_gp.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

484
build/openroad/logs/clk_25_allrams/3_1_place_gp.log

@ -0,0 +1,484 @@ @@ -0,0 +1,484 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1327998 connections.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 460 2720
[INFO GPL-0004] CoreAreaLxLy: 210220 212160
[INFO GPL-0005] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0006] NumInstances: 663999
[INFO GPL-0007] NumPlaceInstances: 398098
[INFO GPL-0008] NumFixedInstances: 265901
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 327254
[INFO GPL-0011] NumPins: 1316213
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 5200000 4609140
[INFO GPL-0014] CoreAreaLxLy: 210220 212160
[INFO GPL-0015] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0016] CoreArea: 19954950880000
[INFO GPL-0017] NonPlaceInstsArea: 332695331200
[INFO GPL-0018] PlaceInstsArea: 8612049638400
[INFO GPL-0019] Util(%): 43.89
[INFO GPL-0020] StdInstsArea: 8612049638400
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace] Iter: 1 CG Error: 0.00530206 HPWL: 3907644220
[InitialPlace] Iter: 2 CG Error: 0.00015285 HPWL: 3898324625
[InitialPlace] Iter: 3 CG Error: 0.00001702 HPWL: 3917260234
[InitialPlace] Iter: 4 CG Error: 0.00000780 HPWL: 3925416216
[InitialPlace] Iter: 5 CG Error: 0.00000820 HPWL: 3924025643
[INFO GPL-0031] FillerInit: NumGCells: 544679
[INFO GPL-0032] FillerInit: NumGNets: 327254
[INFO GPL-0033] FillerInit: NumGPins: 1316213
[INFO GPL-0023] TargetDensity: 0.60
[INFO GPL-0024] AveragePlaceInstArea: 21632988
[INFO GPL-0025] IdealBinArea: 36054980
[INFO GPL-0026] IdealBinCnt: 553458
[INFO GPL-0027] TotalBinArea: 19954950880000
[INFO GPL-0028] BinCnt: 512 512
[INFO GPL-0029] BinSize: 9335 8155
[INFO GPL-0030] NumBins: 262144
[NesterovSolve] Iter: 1 overflow: 0.998843 HPWL: 1178593019
[NesterovSolve] Iter: 10 overflow: 0.996703 HPWL: 1383833412
[NesterovSolve] Iter: 20 overflow: 0.995116 HPWL: 1485362623
[NesterovSolve] Iter: 30 overflow: 0.994292 HPWL: 1558916158
[NesterovSolve] Iter: 40 overflow: 0.994054 HPWL: 1577173517
[NesterovSolve] Iter: 50 overflow: 0.994082 HPWL: 1572988477
[NesterovSolve] Iter: 60 overflow: 0.994164 HPWL: 1560096761
[NesterovSolve] Iter: 70 overflow: 0.994165 HPWL: 1554774586
[NesterovSolve] Iter: 80 overflow: 0.994077 HPWL: 1558468307
[NesterovSolve] Iter: 90 overflow: 0.994026 HPWL: 1561990551
[NesterovSolve] Iter: 100 overflow: 0.993999 HPWL: 1562744741
[NesterovSolve] Iter: 110 overflow: 0.993947 HPWL: 1563230947
[NesterovSolve] Iter: 120 overflow: 0.993911 HPWL: 1565136404
[NesterovSolve] Iter: 130 overflow: 0.993867 HPWL: 1569193928
[NesterovSolve] Iter: 140 overflow: 0.993766 HPWL: 1575346564
[NesterovSolve] Iter: 150 overflow: 0.993732 HPWL: 1583978189
[NesterovSolve] Iter: 160 overflow: 0.993706 HPWL: 1596952209
[NesterovSolve] Iter: 170 overflow: 0.993623 HPWL: 1618765427
[NesterovSolve] Iter: 180 overflow: 0.993535 HPWL: 1657890635
[NesterovSolve] Iter: 190 overflow: 0.993433 HPWL: 1728669762
[NesterovSolve] Iter: 200 overflow: 0.993256 HPWL: 1831684995
[NesterovSolve] Iter: 210 overflow: 0.992831 HPWL: 1955699898
[NesterovSolve] Iter: 220 overflow: 0.992243 HPWL: 2103550626
[NesterovSolve] Iter: 230 overflow: 0.991216 HPWL: 2275006532
[NesterovSolve] Iter: 240 overflow: 0.989654 HPWL: 2468206176
[NesterovSolve] Iter: 250 overflow: 0.987157 HPWL: 2696734652
[NesterovSolve] Iter: 260 overflow: 0.983796 HPWL: 2981765708
[NesterovSolve] Iter: 270 overflow: 0.979336 HPWL: 3352239567
[NesterovSolve] Iter: 280 overflow: 0.974187 HPWL: 3837780564
[NesterovSolve] Iter: 290 overflow: 0.966888 HPWL: 4455758135
[NesterovSolve] Iter: 300 overflow: 0.956534 HPWL: 5179118538
[NesterovSolve] Iter: 310 overflow: 0.944754 HPWL: 5975524701
[NesterovSolve] Iter: 320 overflow: 0.931769 HPWL: 6792159301
[NesterovSolve] Iter: 330 overflow: 0.918041 HPWL: 7563895725
[NesterovSolve] Iter: 340 overflow: 0.900089 HPWL: 8247237488
[NesterovSolve] Iter: 350 overflow: 0.874767 HPWL: 8833027362
[NesterovSolve] Iter: 360 overflow: 0.84496 HPWL: 9262026725
[NesterovSolve] Iter: 370 overflow: 0.816831 HPWL: 9723087585
[NesterovSolve] Iter: 380 overflow: 0.780891 HPWL: 10351166790
[NesterovSolve] Iter: 390 overflow: 0.748237 HPWL: 11018587998
[NesterovSolve] Iter: 400 overflow: 0.713132 HPWL: 12227258975
[NesterovSolve] Iter: 410 overflow: 0.672395 HPWL: 13183941296
[NesterovSolve] Iter: 420 overflow: 0.631086 HPWL: 14313278736
[NesterovSolve] Snapshot saved at iter = 427
[NesterovSolve] Iter: 430 overflow: 0.591573 HPWL: 14525530958
[NesterovSolve] Iter: 440 overflow: 0.546674 HPWL: 13604641697
[NesterovSolve] Iter: 450 overflow: 0.50002 HPWL: 12942487503
[NesterovSolve] Iter: 460 overflow: 0.465658 HPWL: 12530988216
[NesterovSolve] Iter: 470 overflow: 0.438527 HPWL: 12363362542
[NesterovSolve] Iter: 480 overflow: 0.411598 HPWL: 11792184906
[NesterovSolve] Iter: 490 overflow: 0.383516 HPWL: 11313374722
[NesterovSolve] Iter: 500 overflow: 0.356781 HPWL: 10882419956
[NesterovSolve] Iter: 510 overflow: 0.332606 HPWL: 10483405942
[NesterovSolve] Iter: 520 overflow: 0.311508 HPWL: 10139151789
[NesterovSolve] Iter: 530 overflow: 0.289899 HPWL: 9861174515
[NesterovSolve] Iter: 540 overflow: 0.262002 HPWL: 9659416789
[NesterovSolve] Iter: 550 overflow: 0.222746 HPWL: 9502611747
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met5
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via L1M1_PR as default.
[INFO GRT-0224] Chose via M1M2_PR as default.
[INFO GRT-0224] Chose via M2M3_PR as default.
[INFO GRT-0224] Chose via M3M4_PR as default.
[INFO GRT-0224] Chose via M4M5_PR as default.
[INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400
[INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 1992109
[INFO GRT-0019] Found 18045 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 68060
[INFO GRT-0017] Processing 3406482 blockages on layer met1.
[INFO GRT-0017] Processing 352 blockages on layer met4.
[INFO GRT-0017] Processing 306 blockages on layer met5.

[INFO GRT-0053] Routing resources analysis:
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 0 0 0.00%
met1 Horizontal 10045020 4932528 50.90%
met2 Vertical 7533765 4522140 39.98%
met3 Horizontal 5022510 3018528 39.90%
met4 Vertical 3013506 1510488 49.88%
met5 Horizontal 1004502 502336 49.99%
---------------------------------------------------------------

[INFO GRT-0104] Minimal overflow 1142 occurring at round 0.
[INFO GRT-0111] Final number of vias: 1822747
[INFO GRT-0112] Final usage 3D: 8509419
[WARNING GRT-0115] Global routing finished with overflow.

[INFO GRT-0096] Final congestion report:
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 0 48 0.00% 0 / 2 / 48
met1 4932528 1296824 26.29% 4 / 0 / 37
met2 4522140 1313654 29.05% 0 / 5 / 833
met3 3018528 265850 8.81% 2 / 0 / 5
met4 1510488 162384 10.75% 0 / 3 / 219
met5 502336 2418 0.48% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 14486020 3041178 20.99% 6 / 10 / 1142

[INFO GRT-0018] Total wirelength: 28766879 um
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 6900 6900
[INFO GPL-0038] TileCnt: 753 668
[INFO GPL-0039] numRoutingLayers: 6
[INFO GPL-0040] NumTiles: 503004
[INFO GPL-0063] TotalRouteOverflowH2: 0.6000000238418579
[INFO GPL-0064] TotalRouteOverflowV2: 92.03334939479828
[INFO GPL-0065] OverflowTileCnt2: 803
[INFO GPL-0066] 0.5%RC: 1.0183735974036332
[INFO GPL-0067] 1.0%RC: 1.0091877158225815
[INFO GPL-0068] 2.0%RC: 1.0045938579112907
[INFO GPL-0069] 5.0%RC: 0.9496705569002577
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 1.0137807
[NesterovSolve] Iter: 560 overflow: 0.187525 HPWL: 9358515093
[NesterovSolve] Iter: 570 overflow: 0.161221 HPWL: 9283610515
[NesterovSolve] Iter: 580 overflow: 0.140208 HPWL: 9193050204
[NesterovSolve] Iter: 590 overflow: 0.123307 HPWL: 9083231317
[NesterovSolve] Iter: 600 overflow: 0.109013 HPWL: 9066029377
[NesterovSolve] Finished with Overflow: 0.099666

==========================================================================
global place report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.22 externalResetVector[1] (net)
0.23 0.11 0.11 v _346224_/B (sky130_fd_sc_hd__nand2_1)
0.09 0.14 0.26 ^ _346224_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.09 0.00 0.26 ^ _404211_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.26 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.10 0.10 library removal time
0.10 data required time
-----------------------------------------------------------------------------
0.10 data required time
-0.26 data arrival time
-----------------------------------------------------------------------------
0.16 slack (MET)


Startpoint: iBusWB_DAT_MISO[8] (input port clocked by clk)
Endpoint: _348151_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[8] (in)
1 0.03 iBusWB_DAT_MISO[8] (net)
0.00 0.00 0.00 ^ _348151_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _348151_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
global place report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[27] (input port clocked by clk)
Endpoint: _404237_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[27] (in)
2 0.76 externalResetVector[27] (net)
2.67 1.34 1.34 v _346252_/B (sky130_fd_sc_hd__nand2_1)
0.47 0.60 1.94 ^ _346252_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000357_ (net)
0.47 0.00 1.94 ^ _404237_/SET_B (sky130_fd_sc_hd__dfbbp_1)
1.94 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _404237_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 39.93 library recovery time
39.93 data required time
-----------------------------------------------------------------------------
39.93 data required time
-1.94 data arrival time
-----------------------------------------------------------------------------
37.99 slack (MET)


Startpoint: _404560_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _404560_/CLK (sky130_fd_sc_hd__dfrtp_1)
7.05 4.15 4.15 ^ _404560_/Q (sky130_fd_sc_hd__dfrtp_1)
7 0.83 dBusWB_CYC (net)
7.05 0.00 4.15 ^ _176631_/A2 (sky130_fd_sc_hd__a31oi_1)
0.87 0.54 4.69 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.87 0.00 4.69 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
59.18 43.79 48.48 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 2.05 _057233_ (net)
59.18 0.11 48.59 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
43.23 45.63 94.22 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.22 _057237_ (net)
43.23 0.01 94.23 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.71 11.09 105.31 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.01 _057243_ (net)
0.71 0.00 105.31 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
1895.01 1381.65 1486.96 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 65.04 _057333_ (net)
1895.02 3.84 1490.81 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
32.87 25946.33 27437.13 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 4.59 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
32.87 3.59 27440.72 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.88 12.98 27453.70 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.10 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.88 0.01 27453.71 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.85 0.40 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.85 0.00 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
27454.11 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.35 19.65 library setup time
19.65 data required time
-----------------------------------------------------------------------------
19.65 data required time
-27454.11 data arrival time
-----------------------------------------------------------------------------
-27434.46 slack (VIOLATED)



==========================================================================
global place report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[27] (input port clocked by clk)
Endpoint: _404237_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[27] (in)
2 0.76 externalResetVector[27] (net)
2.67 1.34 1.34 v _346252_/B (sky130_fd_sc_hd__nand2_1)
0.47 0.60 1.94 ^ _346252_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000357_ (net)
0.47 0.00 1.94 ^ _404237_/SET_B (sky130_fd_sc_hd__dfbbp_1)
1.94 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _404237_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 39.93 library recovery time
39.93 data required time
-----------------------------------------------------------------------------
39.93 data required time
-1.94 data arrival time
-----------------------------------------------------------------------------
37.99 slack (MET)


Startpoint: _404560_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _404560_/CLK (sky130_fd_sc_hd__dfrtp_1)
7.05 4.15 4.15 ^ _404560_/Q (sky130_fd_sc_hd__dfrtp_1)
7 0.83 dBusWB_CYC (net)
7.05 0.00 4.15 ^ _176631_/A2 (sky130_fd_sc_hd__a31oi_1)
0.87 0.54 4.69 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.87 0.00 4.69 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
59.18 43.79 48.48 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 2.05 _057233_ (net)
59.18 0.11 48.59 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
43.23 45.63 94.22 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.22 _057237_ (net)
43.23 0.01 94.23 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.71 11.09 105.31 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.01 _057243_ (net)
0.71 0.00 105.31 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
1895.01 1381.65 1486.96 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 65.04 _057333_ (net)
1895.02 3.84 1490.81 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
32.87 25946.33 27437.13 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 4.59 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
32.87 3.59 27440.72 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.88 12.98 27453.70 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.10 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.88 0.01 27453.71 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.85 0.40 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.85 0.00 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
27454.11 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.35 19.65 library setup time
19.65 data required time
-----------------------------------------------------------------------------
19.65 data required time
-27454.11 data arrival time
-----------------------------------------------------------------------------
-27434.46 slack (VIOLATED)



==========================================================================
global place report_tns
--------------------------------------------------------------------------
tns -64188920.00

==========================================================================
global place report_wns
--------------------------------------------------------------------------
wns -27434.46

==========================================================================
global place report_worst_slack
--------------------------------------------------------------------------
worst slack -27434.46

==========================================================================
global place report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.Do0_FF[6]/CLK ^
0.00 0.00 0.26


==========================================================================
global place report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.06e-01 5.37e-03 9.29e-07 1.12e-01 11.4%
Combinational 7.55e-01 1.12e-01 8.90e-07 8.66e-01 88.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 8.61e-01 1.17e-01 1.82e-06 9.78e-01 100.0%
88.0% 12.0% 0.0%

==========================================================================
global place report_design_area
--------------------------------------------------------------------------
Design area 4959944 u^2 25% utilization.

Elapsed time: 12:51.27[h:]min:sec. CPU time: user 759.70 sys 11.43 (99%). Peak memory: 15006996KB.

2
build/openroad/logs/clk_25_allrams/3_2_place_iop.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

39
build/openroad/logs/clk_25_allrams/3_2_place_iop.log

@ -0,0 +1,39 @@ @@ -0,0 +1,39 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1327998 connections.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0010] Tentative 0 to set up sections.
[INFO PPL-0001] Number of slots 18082
[INFO PPL-0002] Number of I/O 254
[INFO PPL-0003] Number of I/O w/sink 254
[INFO PPL-0004] Number of I/O w/o sink 7
[INFO PPL-0005] Slots per section 200
[INFO PPL-0006] Slots increase factor 0.01
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 308203.00 um.
Elapsed time: 0:11.71[h:]min:sec. CPU time: user 11.15 sys 0.52 (99%). Peak memory: 1549800KB.

2
build/openroad/logs/clk_25_allrams/3_3_resizer.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

76221
build/openroad/logs/clk_25_allrams/3_3_resizer.log

File diff suppressed because it is too large Load Diff

2
build/openroad/logs/clk_25_allrams/3_4_opendp.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

76191
build/openroad/logs/clk_25_allrams/3_4_opendp.log

File diff suppressed because it is too large Load Diff

2
build/openroad/logs/clk_25_allrams/4_1_cts.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

308914
build/openroad/logs/clk_25_allrams/4_1_cts.log

File diff suppressed because it is too large Load Diff

2
build/openroad/logs/clk_25_allrams/4_2_cts_fillcell.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

29
build/openroad/logs/clk_25_allrams/4_2_cts_fillcell.log

@ -0,0 +1,29 @@ @@ -0,0 +1,29 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0094] Created 700000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 715330 components and 2849571 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1430660 connections.
[INFO ODB-0133] Created 378585 nets and 1412715 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO DPL-0001] Placed 1982253 filler instances.
Elapsed time: 0:20.97[h:]min:sec. CPU time: user 19.56 sys 1.05 (98%). Peak memory: 2436392KB.

2
build/openroad/logs/clk_25_allrams/5_1_fastroute.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

78897
build/openroad/logs/clk_25_allrams/5_1_fastroute.log

File diff suppressed because it is too large Load Diff

4
build/openroad/logs/clk_25_allrams/5_2_TritonRoute.json

@ -0,0 +1,4 @@ @@ -0,0 +1,4 @@
{
"drt::wire length::total" : 22781418
, "drt::vias::total" : 3240309
}

1481
build/openroad/logs/clk_25_allrams/5_2_TritonRoute.log

File diff suppressed because it is too large Load Diff

42
build/openroad/logs/clk_25_allrams/6_1_merge.log

@ -0,0 +1,42 @@ @@ -0,0 +1,42 @@
[INFO] Reporting cells prior to loading DEF ...
[INFO] Reading DEF ...
[INFO] Clearing cells...
[INFO] ... preserving 'VIA_L1M1_PR'
[INFO] ... preserving 'VIA_L1M1_PR_R'
[INFO] ... preserving 'VIA_L1M1_PR_M'
[INFO] ... preserving 'VIA_L1M1_PR_MR'
[INFO] ... preserving 'VIA_L1M1_PR_C'
[INFO] ... preserving 'VIA_M1M2_PR'
[INFO] ... preserving 'VIA_M1M2_PR_R'
[INFO] ... preserving 'VIA_M1M2_PR_M'
[INFO] ... preserving 'VIA_M1M2_PR_MR'
[INFO] ... preserving 'VIA_M1M2_PR_C'
[INFO] ... preserving 'VIA_M2M3_PR'
[INFO] ... preserving 'VIA_M2M3_PR_R'
[INFO] ... preserving 'VIA_M2M3_PR_M'
[INFO] ... preserving 'VIA_M2M3_PR_MR'
[INFO] ... preserving 'VIA_M2M3_PR_C'
[INFO] ... preserving 'VIA_M3M4_PR'
[INFO] ... preserving 'VIA_M3M4_PR_R'
[INFO] ... preserving 'VIA_M3M4_PR_M'
[INFO] ... preserving 'VIA_M3M4_PR_MR'
[INFO] ... preserving 'VIA_M3M4_PR_C'
[INFO] ... preserving 'VIA_M4M5_PR'
[INFO] ... preserving 'VIA_M4M5_PR_R'
[INFO] ... preserving 'VIA_M4M5_PR_M'
[INFO] ... preserving 'VIA_M4M5_PR_MR'
[INFO] ... preserving 'VIA_M4M5_PR_C'
[INFO] ... preserving 'VIA_via_1600x480'
[INFO] ... preserving 'VIA_via2_1600x480'
[INFO] ... preserving 'VIA_via3_1600x480'
[INFO] ... preserving 'VIA_via4_1600x1600'
[INFO] Merging GDS/OAS files...
./platforms/sky130hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'A2P_WB'
INFO: Reading config file: ./platforms/sky130hd/fill.json
[INFO] Checking for missing cell from GDS/OAS...
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] Checking for orphan cell in the final layout...
[INFO] No orphan cells
[INFO] Writing out GDS/OAS 'results/sky130hd/a2p/base/6_1_merged.gds'
Elapsed time: 0:54.67[h:]min:sec. CPU time: user 51.48 sys 2.67 (99%). Peak memory: 6583756KB.

2
build/openroad/logs/clk_25_allrams/6_report.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

78509
build/openroad/logs/clk_25_allrams/6_report.log

File diff suppressed because it is too large Load Diff

80184
build/openroad/logs/clk_40_allrams/1_1_yosys.log

File diff suppressed because it is too large Load Diff

2
build/openroad/logs/clk_40_allrams/2_1_floorplan.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

320
build/openroad/logs/clk_40_allrams/2_1_floorplan.log

@ -0,0 +1,320 @@ @@ -0,0 +1,320 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[WTF] clk_period=25.0
number instances in verilog is 432348
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 34250 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um

==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 v _346224_/B (sky130_fd_sc_hd__nand2_1)
0.05 0.05 0.05 ^ _346224_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.05 0.01 0.06 ^ _404211_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.06 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.11 0.11 library removal time
0.11 data required time
-----------------------------------------------------------------------------
0.11 data required time
-0.06 data arrival time
-----------------------------------------------------------------------------
-0.05 slack (VIOLATED)


Startpoint: iBusWB_DAT_MISO[0] (input port clocked by clk)
Endpoint: _348143_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[0] (in)
1 0.00 iBusWB_DAT_MISO[0] (net)
0.00 0.00 0.00 ^ _348143_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _348143_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 25.00 25.00 clock clk (rise edge)
0.00 25.00 clock network delay (ideal)
0.00 25.00 clock reconvergence pessimism
25.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 24.93 library recovery time
24.93 data required time
-----------------------------------------------------------------------------
24.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
24.85 slack (MET)


Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
7 0.02 _057091_ (net)
0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _057181_ (net)
0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 0.92 _057233_ (net)
26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.10 _057237_ (net)
8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.00 _057243_ (net)
0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 33.23 _057333_ (net)
955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6504.75 data arrival time

0.00 12.50 12.50 clock clk' (rise edge)
0.00 12.50 clock network delay (ideal)
0.00 12.50 clock reconvergence pessimism
12.50 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 12.31 library setup time
12.31 data required time
-----------------------------------------------------------------------------
12.31 data required time
-6504.75 data arrival time
-----------------------------------------------------------------------------
-6492.44 slack (VIOLATED)



==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _404211_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 25.00 25.00 clock clk (rise edge)
0.00 25.00 clock network delay (ideal)
0.00 25.00 clock reconvergence pessimism
25.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 24.93 library recovery time
24.93 data required time
-----------------------------------------------------------------------------
24.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
24.85 slack (MET)


Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
7 0.02 _057091_ (net)
0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _057181_ (net)
0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
2 0.01 _057182_ (net)
0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
365 0.92 _057233_ (net)
26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
42 0.10 _057237_ (net)
8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
2 0.00 _057243_ (net)
0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
9416 33.23 _057333_ (net)
955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6504.75 data arrival time

0.00 12.50 12.50 clock clk' (rise edge)
0.00 12.50 clock network delay (ideal)
0.00 12.50 clock reconvergence pessimism
12.50 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 12.31 library setup time
12.31 data required time
-----------------------------------------------------------------------------
12.31 data required time
-6504.75 data arrival time
-----------------------------------------------------------------------------
-6492.44 slack (VIOLATED)



==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -14699485.00

==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -6492.44

==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -6492.44

==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[0]/CLK ^
0.00 0.00 0.26


==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.60e-01 4.65e-03 9.29e-07 1.65e-01 21.9%
Combinational 5.52e-01 3.37e-02 8.90e-07 5.85e-01 78.1%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 7.12e-01 3.83e-02 1.82e-06 7.50e-01 100.0%
94.9% 5.1% 0.0%

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 4627248 u^2 23% utilization.

Elapsed time: 2:33.21[h:]min:sec. CPU time: user 152.64 sys 0.52 (99%). Peak memory: 1397284KB.

2
build/openroad/logs/clk_40_allrams/2_2_floorplan_io.json

@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
{
}

27
build/openroad/logs/clk_40_allrams/2_2_floorplan_io.log

@ -0,0 +1,27 @@ @@ -0,0 +1,27 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
Elapsed time: 0:05.68[h:]min:sec. CPU time: user 5.33 sys 0.30 (99%). Peak memory: 591324KB.

2
build/openroad/logs/clk_40_allrams/2_3_tdms.json

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{
}

25
build/openroad/logs/clk_40_allrams/2_3_tdms_place.log

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
[INFO ODB-0133] Created 327254 nets and 1315959 connections.