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arci

master
wtf 1 year ago
parent
commit
4948e96692
  1. 11
      software/arci/refactor/arcigen.py
  2. 1
      software/arci/refactor/ops_div.py
  3. 36
      software/arci/refactor/ops_mov.py
  4. 293
      software/arci/refactor/simple3.s
  5. 165
      software/arci/refactor/simple3.tst

11
software/arci/refactor/arcigen.py

@ -41,6 +41,7 @@ from ctypes import c_uint32 @@ -41,6 +41,7 @@ from ctypes import c_uint32
from arch import *
from ops_add import *
from ops_div import *
from ops_mov import *

# -------------------------------------------------------------------------------------------------
# Initialization
@ -56,7 +57,7 @@ magic = "0x08675309" @@ -56,7 +57,7 @@ magic = "0x08675309"
savespr = "tar"

tplFileAsm = 'arcitst.tpl'
tstName = 'simple2'
tstName = 'simple3'
outFileTst = f'{tstName}.tst'
outFileAsm = f'{tstName}.s'

@ -153,6 +154,7 @@ divw = DivW(facs) @@ -153,6 +154,7 @@ divw = DivW(facs)
divw_r = DivW(facs, rc= True)
divwo = DivW(facs, oe=True)
divwo_r = DivW(facs, rc=True, oe=True)
mfcr = MFCR(facs)

# -------------------------------------------------------------------------------------------------
# Do something
@ -168,6 +170,7 @@ lines.append('\n* Instructions\n') @@ -168,6 +170,7 @@ lines.append('\n* Instructions\n')
# phony dumb test
def addToTest(op):
op.addToStream(ops).print(lines)

addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines)
addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines)
addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines)
@ -177,7 +180,11 @@ addi.do(facs.r6, facs.r0, 10).addToStream(ops).print(lines) @@ -177,7 +180,11 @@ addi.do(facs.r6, facs.r0, 10).addToStream(ops).print(lines)
addi.do(facs.r7, facs.r0, -5).addToStream(ops).print(lines)
addToTest(divw.do(facs.r8, facs.r6, facs.r7))
addToTest(divw_r.do(facs.r9, facs.r6, facs.r7))

addToTest(mfcr.do(facs.r31))
addToTest(divw_r.do(facs.r10, facs.r7, facs.r6))
addToTest(mfcr.do(facs.r30))
addToTest(divw_r.do(facs.r11, facs.r6, facs.r6))
addToTest(mfcr.do(facs.r30))

lines.append('\n* Results (Changed)\n')
printSPR(chg=True)

1
software/arci/refactor/ops_div.py

@ -36,6 +36,7 @@ class DivW(Op): @@ -36,6 +36,7 @@ class DivW(Op):
self.rt = rt
self.ra = ra
self.rb = rb
#wtf is this wrong for -5/10? returning 0x80000000, not 0x00000000
res = c_uint32(c_int32(gpr[ra].value).value // c_int32(gpr[rb].value).value).value
gpr[rt].value = res
gpr[ra].ref = True

36
software/arci/refactor/ops_mov.py

@ -0,0 +1,36 @@ @@ -0,0 +1,36 @@
# def MTCRF = M"011111-----0---------0010010000-" //121
# def MTOCRF = M"011111-----1---------0010010000-" //121
# def MCRF = M"010011---------------0000000000-" // 41
# def MCRXRX = M"011111---------------1001000000-" //120
# def MFCR = M"011111-----0---------0000010011-" //122
# def MFOCRF = M"011111-----1---------0000010011-" //122
# def MTSPR = M"011111---------------0111010011-" // 117
# def MFSPR = M"011111---------------0101010011-" // 119
# def MTMSR = M"011111---------------0010010010-" // 977
# def MFMSR = M"011111---------------0001010011-" // 979

from arch import Op

class MFCR(Op):

def __init__(self, facs):
self.name = 'mfcr'
self.facs = facs

def do(self, rt):
gpr = self.facs.gpr
cia = self.facs.cia
cr = self.facs.cr
self.rt = rt
res = cr.value
gpr[rt].value = res
cr.ref = True
gpr[rt].chg = True
self.cia = cia.value
cia.value += 4
self.nia = cia.value
cia.chg = True
self.op = f'{self.name:10s} {self.rt}'
self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment())]
self.res.append((cia.rname, self.nia, cia.comment()))
return self

293
software/arci/refactor/simple3.s

@ -0,0 +1,293 @@ @@ -0,0 +1,293 @@
# architst

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_name: .asciz "simple3"
tst_info: .asciz "wtf"

.set SAVESPR,tar
.set MAGIC,0x08675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .long 0x00000000
init_r1: .long 0x00000000
init_r2: .long 0x00000000
init_r3: .long 0x00000000
init_r4: .long 0x00000000
init_r5: .long 0x00000000
init_r6: .long 0x00000000
init_r7: .long 0x00000000
init_r8: .long 0x00000000
init_r9: .long 0x00000000
init_r10: .long 0x00000000
init_r11: .long 0x00000000
init_r12: .long 0x00000000
init_r13: .long 0x00000000
init_r14: .long 0x00000000
init_r15: .long 0x00000000
init_r16: .long 0x00000000
init_r17: .long 0x00000000
init_r18: .long 0x00000000
init_r19: .long 0x00000000
init_r20: .long 0x00000000
init_r21: .long 0x00000000
init_r22: .long 0x00000000
init_r23: .long 0x00000000
init_r24: .long 0x00000000
init_r25: .long 0x00000000
init_r26: .long 0x00000000
init_r27: .long 0x00000000
init_r28: .long 0x00000000
init_r29: .long 0x00000000
init_r30: .long 0x00000000
init_r31: .long 0x00000000

init_cr: .long 0x00000000
init_xer: .long 0x00000000
init_ctr: .long 0xF0000000
init_lr: .long 0x00000000
init_tar: .long 0x00000000

save_r1: .long 0

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# init test regs
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

b tst_start

# -------------------------------------------------------------------------------------------------
.align 5
tst_start:

# -------------------------------------------------------------------------------------------------
addi r3,r3,1
addi r3,r3,1
addi r3,r3,1
addi r4,r0,-3
add. r4,r4,r3
addi r6,r0,10
addi r7,r0,-5
divw r8,r6,r7
divw. r9,r6,r7
mfcr r31
divw. r10,r7,r6
mfcr r30
divw. r11,r6,r6
mfcr r30
# -------------------------------------------------------------------------------------------------

tst_end:
b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

b tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .long 0xFFFFFFFF
rslt_r1: .long 0xFFFFFFFF
rslt_r2: .long 0xFFFFFFFF
rslt_r3: .long 0xFFFFFFFF
rslt_r4: .long 0xFFFFFFFF
rslt_r5: .long 0xFFFFFFFF
rslt_r6: .long 0xFFFFFFFF
rslt_r7: .long 0xFFFFFFFF
rslt_r8: .long 0xFFFFFFFF
rslt_r9: .long 0xFFFFFFFF
rslt_r10: .long 0xFFFFFFFF
rslt_r11: .long 0xFFFFFFFF
rslt_r12: .long 0xFFFFFFFF
rslt_r13: .long 0xFFFFFFFF
rslt_r14: .long 0xFFFFFFFF
rslt_r15: .long 0xFFFFFFFF
rslt_r16: .long 0xFFFFFFFF
rslt_r17: .long 0xFFFFFFFF
rslt_r18: .long 0xFFFFFFFF
rslt_r19: .long 0xFFFFFFFF
rslt_r20: .long 0xFFFFFFFF
rslt_r21: .long 0xFFFFFFFF
rslt_r22: .long 0xFFFFFFFF
rslt_r23: .long 0xFFFFFFFF
rslt_r24: .long 0xFFFFFFFF
rslt_r25: .long 0xFFFFFFFF
rslt_r26: .long 0xFFFFFFFF
rslt_r27: .long 0xFFFFFFFF
rslt_r28: .long 0xFFFFFFFF
rslt_r29: .long 0xFFFFFFFF
rslt_r30: .long 0xFFFFFFFF
rslt_r31: .long 0xFFFFFFFF

rslt_cr: .long 0xFFFFFFFF
rslt_xer: .long 0xFFFFFFFF
rslt_ctr: .long 0xFFFFFFFF
rslt_lr: .long 0xFFFFFFFF
rslt_tar: .long 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .long 0x00000000
expt_r1: .long 0x00000000
expt_r2: .long 0x00000000
expt_r3: .long 0x00000003
expt_r4: .long 0x00000000
expt_r5: .long 0x00000000
expt_r6: .long 0x0000000A
expt_r7: .long 0xFFFFFFFB
expt_r8: .long 0xFFFFFFFE
expt_r9: .long 0xFFFFFFFE
expt_r10: .long 0xFFFFFFFF
expt_r11: .long 0x00000001
expt_r12: .long 0x00000000
expt_r13: .long 0x00000000
expt_r14: .long 0x00000000
expt_r15: .long 0x00000000
expt_r16: .long 0x00000000
expt_r17: .long 0x00000000
expt_r18: .long 0x00000000
expt_r19: .long 0x00000000
expt_r20: .long 0x00000000
expt_r21: .long 0x00000000
expt_r22: .long 0x00000000
expt_r23: .long 0x00000000
expt_r24: .long 0x00000000
expt_r25: .long 0x00000000
expt_r26: .long 0x00000000
expt_r27: .long 0x00000000
expt_r28: .long 0x00000000
expt_r29: .long 0x00000000
expt_r30: .long 0x40000000
expt_r31: .long 0x80000000

expt_cr: .long 0x40000000
expt_xer: .long 0x00000000
expt_ctr: .long 0xF0000000
expt_lr: .long 0x00000000
expt_tar: .long 0x00000000

165
software/arci/refactor/simple3.tst

@ -0,0 +1,165 @@ @@ -0,0 +1,165 @@

* arci v.0.0001
* -----------------------------------------------------------------------------------------
* Generated: Nov 20 2021 10:53:39 PM GMT
*

* Initialization

R CIA 00120000
R CR 00000000 * F0:0 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R XER 00000000
R CTR F0000000
R LR 00000000
R TAR 00000000
R R00 00000000 * 0
R R01 00000000 * 0
R R02 00000000 * 0
R R03 00000000 * 0
R R04 00000000 * 0
R R05 00000000 * 0
R R06 00000000 * 0
R R07 00000000 * 0
R R08 00000000 * 0
R R09 00000000 * 0
R R10 00000000 * 0
R R11 00000000 * 0
R R12 00000000 * 0
R R13 00000000 * 0
R R14 00000000 * 0
R R15 00000000 * 0
R R16 00000000 * 0
R R17 00000000 * 0
R R18 00000000 * 0
R R19 00000000 * 0
R R20 00000000 * 0
R R21 00000000 * 0
R R22 00000000 * 0
R R23 00000000 * 0
R R24 00000000 * 0
R R25 00000000 * 0
R R26 00000000 * 0
R R27 00000000 * 0
R R28 00000000 * 0
R R29 00000000 * 0
R R30 00000000 * 0
R R31 00000000 * 0

* Instructions

I 00120000 addi r3,r3,1
R R03 00000001 * 1
R CIA 00120004

I 00120004 addi r3,r3,1
R R03 00000002 * 2
R CIA 00120008

I 00120008 addi r3,r3,1
R R03 00000003 * 3
R CIA 0012000C

I 0012000C addi r4,r0,-3
R R04 FFFFFFFD * 4294967293 -3
R CIA 00120010

I 00120010 add. r4,r4,r3
R R04 00000000 * 0
R CR 20000000 * F0:2 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R CIA 00120014

I 00120014 addi r6,r0,10
R R06 0000000A * 10
R CIA 00120018

I 00120018 addi r7,r0,-5
R R07 FFFFFFFB * 4294967291 -5
R CIA 0012001C

I 0012001C divw r8,r6,r7
R R08 FFFFFFFE * 4294967294 -2
R CIA 00120020

I 00120020 divw. r9,r6,r7
R R09 FFFFFFFE * 4294967294 -2
R CR 80000000 * F0:8 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R CIA 00120024

I 00120024 mfcr r31
R R31 80000000 * 2147483648 -2147483648
R CIA 00120028

I 00120028 divw. r10,r7,r6
R R10 FFFFFFFF * 4294967295 -1
R CR 80000000 * F0:8 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R CIA 0012002C

I 0012002C mfcr r30
R R30 80000000 * 2147483648 -2147483648
R CIA 00120030

I 00120030 divw. r11,r6,r6
R R11 00000001 * 1
R CR 40000000 * F0:4 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R CIA 00120034

I 00120034 mfcr r30
R R30 40000000 * 1073741824
R CIA 00120038


* Results (Changed)

R CIA 00120038
R CR 40000000 * F0:4 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R R03 00000003 * 3
R R04 00000000 * 0
R R06 0000000A * 10
R R07 FFFFFFFB * 4294967291 -5
R R08 FFFFFFFE * 4294967294 -2
R R09 FFFFFFFE * 4294967294 -2
R R10 FFFFFFFF * 4294967295 -1
R R11 00000001 * 1
R R30 40000000 * 1073741824
R R31 80000000 * 2147483648 -2147483648

* Results

R CIA 00120038
R CR 40000000 * F0:4 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R XER 00000000
R CTR F0000000
R LR 00000000
R TAR 00000000
R R00 00000000 * 0
R R01 00000000 * 0
R R02 00000000 * 0
R R03 00000003 * 3
R R04 00000000 * 0
R R05 00000000 * 0
R R06 0000000A * 10
R R07 FFFFFFFB * 4294967291 -5
R R08 FFFFFFFE * 4294967294 -2
R R09 FFFFFFFE * 4294967294 -2
R R10 FFFFFFFF * 4294967295 -1
R R11 00000001 * 1
R R12 00000000 * 0
R R13 00000000 * 0
R R14 00000000 * 0
R R15 00000000 * 0
R R16 00000000 * 0
R R17 00000000 * 0
R R18 00000000 * 0
R R19 00000000 * 0
R R20 00000000 * 0
R R21 00000000 * 0
R R22 00000000 * 0
R R23 00000000 * 0
R R24 00000000 * 0
R R25 00000000 * 0
R R26 00000000 * 0
R R27 00000000 * 0
R R28 00000000 * 0
R R29 00000000 * 0
R R30 40000000 * 1073741824
R R31 80000000 * 2147483648 -2147483648
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