or logs
wtf
2 years ago
parent
637bf2e68b
commit
4f67c011e4
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
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{
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}
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@ -0,0 +1,320 @@
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OpenROAD v2.0-1901-g6157d4945
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This program is licensed under the BSD-3 license. See the LICENSE file for details.
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Components of this program may be licensed under more restrictive licenses which must be honored.
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[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
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[INFO ODB-0223] Created 11 technology layers
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[INFO ODB-0224] Created 25 technology vias
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[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
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[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
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[INFO ODB-0225] Created 437 library cells
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[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
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[WTF] clk_period=40.0
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number instances in verilog is 432348
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[INFO IFP-0001] Added 1535 rows of 10390 sites.
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[INFO RSZ-0026] Removed 34250 buffers.
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Default units for flow
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time 1ns
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capacitance 1pF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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==========================================================================
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floorplan final report_checks -path_delay min
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--------------------------------------------------------------------------
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Startpoint: externalResetVector[1] (input port clocked by clk)
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Endpoint: _404211_ (removal check against rising-edge clock clk)
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Path Group: **async_default**
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 0.00 v externalResetVector[1] (in)
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2 0.00 externalResetVector[1] (net)
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0.00 0.00 0.00 v _346224_/B (sky130_fd_sc_hd__nand2_1)
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0.05 0.05 0.05 ^ _346224_/Y (sky130_fd_sc_hd__nand2_1)
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1 0.00 _000305_ (net)
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0.05 0.01 0.06 ^ _404211_/SET_B (sky130_fd_sc_hd__dfbbp_1)
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0.06 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
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0.11 0.11 library removal time
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0.11 data required time
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-----------------------------------------------------------------------------
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0.11 data required time
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-0.06 data arrival time
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-----------------------------------------------------------------------------
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-0.05 slack (VIOLATED)
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Startpoint: iBusWB_DAT_MISO[0] (input port clocked by clk)
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Endpoint: _348143_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 0.00 ^ iBusWB_DAT_MISO[0] (in)
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1 0.00 iBusWB_DAT_MISO[0] (net)
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0.00 0.00 0.00 ^ _348143_/D (sky130_fd_sc_hd__dfxtp_1)
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0.00 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ _348143_/CLK (sky130_fd_sc_hd__dfxtp_1)
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-0.03 -0.03 library hold time
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-0.03 data required time
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-----------------------------------------------------------------------------
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-0.03 data required time
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-0.00 data arrival time
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-----------------------------------------------------------------------------
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0.03 slack (MET)
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==========================================================================
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floorplan final report_checks -path_delay max
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--------------------------------------------------------------------------
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Startpoint: externalResetVector[1] (input port clocked by clk)
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Endpoint: _404211_ (recovery check against rising-edge clock clk)
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Path Group: **async_default**
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 0.00 ^ externalResetVector[1] (in)
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2 0.00 externalResetVector[1] (net)
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0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
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0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
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1 0.00 _000304_ (net)
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0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
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0.07 data arrival time
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0.00 40.00 40.00 clock clk (rise edge)
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0.00 40.00 clock network delay (ideal)
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0.00 40.00 clock reconvergence pessimism
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40.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
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-0.07 39.93 library recovery time
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39.93 data required time
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-----------------------------------------------------------------------------
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39.93 data required time
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-0.07 data arrival time
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-----------------------------------------------------------------------------
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39.85 slack (MET)
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Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
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Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
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(rising clock gating-check end-point clocked by clk')
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
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1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
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45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
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1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
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0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
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7 0.02 _057091_ (net)
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0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
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0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
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1 0.00 _057181_ (net)
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0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
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0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
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2 0.01 _057182_ (net)
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0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
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26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
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365 0.92 _057233_ (net)
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26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
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8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
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42 0.10 _057237_ (net)
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8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
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0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
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2 0.00 _057243_ (net)
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0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
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955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
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9416 33.23 _057333_ (net)
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955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
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21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
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1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
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21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
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0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
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8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
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0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
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0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
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1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
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0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
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6504.75 data arrival time
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0.00 20.00 20.00 clock clk' (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
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-0.19 19.81 library setup time
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19.81 data required time
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-----------------------------------------------------------------------------
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19.81 data required time
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-6504.75 data arrival time
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-----------------------------------------------------------------------------
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-6484.94 slack (VIOLATED)
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==========================================================================
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floorplan final report_checks -unconstrained
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--------------------------------------------------------------------------
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Startpoint: externalResetVector[1] (input port clocked by clk)
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Endpoint: _404211_ (recovery check against rising-edge clock clk)
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Path Group: **async_default**
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 0.00 ^ externalResetVector[1] (in)
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2 0.00 externalResetVector[1] (net)
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0.00 0.00 0.00 ^ _346189_/A_N (sky130_fd_sc_hd__nand2b_1)
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0.04 0.07 0.07 ^ _346189_/Y (sky130_fd_sc_hd__nand2b_1)
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1 0.00 _000304_ (net)
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0.04 0.00 0.07 ^ _404211_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
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0.07 data arrival time
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0.00 40.00 40.00 clock clk (rise edge)
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0.00 40.00 clock network delay (ideal)
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0.00 40.00 clock reconvergence pessimism
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40.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
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-0.07 39.93 library recovery time
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39.93 data required time
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-----------------------------------------------------------------------------
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39.93 data required time
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-0.07 data arrival time
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-----------------------------------------------------------------------------
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39.85 slack (MET)
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Startpoint: _359636_ (rising edge-triggered flip-flop clocked by clk)
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Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
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(rising clock gating-check end-point clocked by clk')
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ _359636_/CLK (sky130_fd_sc_hd__dfxtp_1)
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1.67 1.43 1.43 ^ _359636_/Q (sky130_fd_sc_hd__dfxtp_1)
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45 0.18 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
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1.67 0.00 1.44 ^ _176469_/A (sky130_fd_sc_hd__nor2b_1)
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0.34 0.32 1.75 v _176469_/Y (sky130_fd_sc_hd__nor2b_1)
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7 0.02 _057091_ (net)
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0.34 0.00 1.75 v _176630_/B1 (sky130_fd_sc_hd__a211oi_1)
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0.20 0.31 2.06 ^ _176630_/Y (sky130_fd_sc_hd__a211oi_1)
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1 0.00 _057181_ (net)
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0.20 0.00 2.07 ^ _176631_/B1 (sky130_fd_sc_hd__a31oi_1)
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0.09 0.08 2.15 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
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2 0.01 _057182_ (net)
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0.09 0.00 2.15 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
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26.48 19.76 21.91 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
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365 0.92 _057233_ (net)
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26.48 0.00 21.91 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
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8.42 10.11 32.02 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
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42 0.10 _057237_ (net)
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8.42 0.00 32.02 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
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0.17 2.38 34.40 v _176698_/X (sky130_fd_sc_hd__a22o_1)
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2 0.00 _057243_ (net)
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0.17 0.00 34.41 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
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955.00 714.13 748.54 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
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9416 33.23 _057333_ (net)
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955.00 0.00 748.54 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
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21.05 5747.95 6496.49 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
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1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
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21.05 0.00 6496.49 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
|
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0.68 7.89 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
|
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8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
|
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0.68 0.00 6504.39 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
|
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0.20 0.36 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
|
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1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
|
||||
0.20 0.00 6504.75 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
|
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6504.75 data arrival time
|
||||
|
||||
0.00 20.00 20.00 clock clk' (rise edge)
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||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
|
||||
-0.19 19.81 library setup time
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19.81 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
19.81 data required time
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||||
-6504.75 data arrival time
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||||
-----------------------------------------------------------------------------
|
||||
-6484.94 slack (VIOLATED)
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|
||||
|
||||
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==========================================================================
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floorplan final report_tns
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--------------------------------------------------------------------------
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tns -13826056.00
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==========================================================================
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floorplan final report_wns
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--------------------------------------------------------------------------
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wns -6484.94
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==========================================================================
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floorplan final report_worst_slack
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--------------------------------------------------------------------------
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worst slack -6484.94
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==========================================================================
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floorplan final report_clock_skew
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--------------------------------------------------------------------------
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Clock clk
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Latency CRPR Skew
|
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IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].genblk1.STORAGE/GATE ^
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||||
0.26
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IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[0]/CLK ^
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0.00 0.00 0.26
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|
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==========================================================================
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floorplan final report_power
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||||
--------------------------------------------------------------------------
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Group Internal Switching Leakage Total
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||||
Power Power Power Power
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||||
----------------------------------------------------------------
|
||||
Sequential 1.00e-01 2.91e-03 9.29e-07 1.03e-01 22.0%
|
||||
Combinational 3.45e-01 2.11e-02 8.90e-07 3.66e-01 78.1%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 4.45e-01 2.40e-02 1.82e-06 4.69e-01 100.0%
|
||||
94.9% 5.1% 0.0%
|
||||
|
||||
==========================================================================
|
||||
floorplan final report_design_area
|
||||
--------------------------------------------------------------------------
|
||||
Design area 4627248 u^2 23% utilization.
|
||||
|
||||
Elapsed time: 2:28.41[h:]min:sec. CPU time: user 147.85 sys 0.52 (99%). Peak memory: 1319716KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,27 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
|
||||
Found 0 macro blocks.
|
||||
Using 1u default distance from corners.
|
||||
Using 2 tracks default min distance between IO pins.
|
||||
[INFO PPL-0007] Random pin placement.
|
||||
Elapsed time: 0:05.59[h:]min:sec. CPU time: user 5.30 sys 0.26 (99%). Peak memory: 591184KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,25 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
|
||||
[WTF] clk_period=40.0
|
||||
No macros found: Skipping global_placement
|
||||
Elapsed time: 0:05.66[h:]min:sec. CPU time: user 5.27 sys 0.36 (99%). Peak memory: 575116KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,25 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
|
||||
[WTF] clk_period=40.0
|
||||
No macros found: Skipping macro_placement
|
||||
Elapsed time: 0:05.68[h:]min:sec. CPU time: user 5.45 sys 0.20 (99%). Peak memory: 575012KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,28 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 398098 components and 2112445 component-terminals.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
|
||||
[WARNING TAP-0014] endcap_cpp option is deprecated.
|
||||
[INFO TAP-0001] Found 0 macro blocks.
|
||||
[INFO TAP-0002] Original rows: 1535
|
||||
[INFO TAP-0003] Created 0 rows for a total of 1535 rows.
|
||||
[INFO TAP-0005] Inserted 265901 tapcells.
|
||||
Elapsed time: 0:05.89[h:]min:sec. CPU time: user 5.69 sys 0.17 (99%). Peak memory: 427276KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,47 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0094] Created 400000 Insts
|
||||
[INFO ODB-0094] Created 500000 Insts
|
||||
[INFO ODB-0094] Created 600000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
|
||||
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
|
||||
config: ./platforms/sky130hd/pdn.cfg
|
||||
[INFO PDN-0008] Design name is A2P_WB.
|
||||
[INFO PDN-0009] Reading technology data.
|
||||
[INFO PDN-0011] ****** INFO ******
|
||||
Type: stdcell, grid
|
||||
Stdcell Rails
|
||||
Layer: met1 - width: 0.480 pitch: 5.440 offset: 0.000
|
||||
Straps
|
||||
Layer: met4 - width: 1.600 pitch: 27.140 offset: 13.570
|
||||
Layer: met5 - width: 1.600 pitch: 27.200 offset: 13.600
|
||||
Connect: {met1 met4} {met4 met5}
|
||||
Type: macro, CORE_macro_grid_1
|
||||
Macro orientation: R0 R180 MX MY
|
||||
Connect: {met4_PIN_ver met5}
|
||||
Type: macro, CORE_macro_grid_2
|
||||
Macro orientation: R90 R270 MXR90 MYR90
|
||||
Connect: {met4_PIN_hor met5}
|
||||
[INFO PDN-0012] **** END INFO ****
|
||||
[INFO PDN-0013] Inserting stdcell grid - grid.
|
||||
[INFO PDN-0015] Writing to database.
|
||||
Elapsed time: 0:45.36[h:]min:sec. CPU time: user 44.04 sys 1.27 (99%). Peak memory: 3756272KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,484 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0094] Created 400000 Insts
|
||||
[INFO ODB-0094] Created 500000 Insts
|
||||
[INFO ODB-0094] Created 600000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 1327998 connections.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
|
||||
[INFO GPL-0002] DBU: 1000
|
||||
[INFO GPL-0003] SiteSize: 460 2720
|
||||
[INFO GPL-0004] CoreAreaLxLy: 210220 212160
|
||||
[INFO GPL-0005] CoreAreaUxUy: 4989620 4387360
|
||||
[INFO GPL-0006] NumInstances: 663999
|
||||
[INFO GPL-0007] NumPlaceInstances: 398098
|
||||
[INFO GPL-0008] NumFixedInstances: 265901
|
||||
[INFO GPL-0009] NumDummyInstances: 0
|
||||
[INFO GPL-0010] NumNets: 327254
|
||||
[INFO GPL-0011] NumPins: 1316213
|
||||
[INFO GPL-0012] DieAreaLxLy: 0 0
|
||||
[INFO GPL-0013] DieAreaUxUy: 5200000 4609140
|
||||
[INFO GPL-0014] CoreAreaLxLy: 210220 212160
|
||||
[INFO GPL-0015] CoreAreaUxUy: 4989620 4387360
|
||||
[INFO GPL-0016] CoreArea: 19954950880000
|
||||
[INFO GPL-0017] NonPlaceInstsArea: 332695331200
|
||||
[INFO GPL-0018] PlaceInstsArea: 8612049638400
|
||||
[INFO GPL-0019] Util(%): 43.89
|
||||
[INFO GPL-0020] StdInstsArea: 8612049638400
|
||||
[INFO GPL-0021] MacroInstsArea: 0
|
||||
[InitialPlace] Iter: 1 CG Error: 0.00530206 HPWL: 3907644220
|
||||
[InitialPlace] Iter: 2 CG Error: 0.00015285 HPWL: 3898324625
|
||||
[InitialPlace] Iter: 3 CG Error: 0.00001702 HPWL: 3917260234
|
||||
[InitialPlace] Iter: 4 CG Error: 0.00000780 HPWL: 3925416216
|
||||
[InitialPlace] Iter: 5 CG Error: 0.00000820 HPWL: 3924025643
|
||||
[INFO GPL-0031] FillerInit: NumGCells: 544679
|
||||
[INFO GPL-0032] FillerInit: NumGNets: 327254
|
||||
[INFO GPL-0033] FillerInit: NumGPins: 1316213
|
||||
[INFO GPL-0023] TargetDensity: 0.60
|
||||
[INFO GPL-0024] AveragePlaceInstArea: 21632988
|
||||
[INFO GPL-0025] IdealBinArea: 36054980
|
||||
[INFO GPL-0026] IdealBinCnt: 553458
|
||||
[INFO GPL-0027] TotalBinArea: 19954950880000
|
||||
[INFO GPL-0028] BinCnt: 512 512
|
||||
[INFO GPL-0029] BinSize: 9335 8155
|
||||
[INFO GPL-0030] NumBins: 262144
|
||||
[NesterovSolve] Iter: 1 overflow: 0.998843 HPWL: 1178593019
|
||||
[NesterovSolve] Iter: 10 overflow: 0.996703 HPWL: 1383833412
|
||||
[NesterovSolve] Iter: 20 overflow: 0.995116 HPWL: 1485362623
|
||||
[NesterovSolve] Iter: 30 overflow: 0.994292 HPWL: 1558916158
|
||||
[NesterovSolve] Iter: 40 overflow: 0.994054 HPWL: 1577173517
|
||||
[NesterovSolve] Iter: 50 overflow: 0.994082 HPWL: 1572988477
|
||||
[NesterovSolve] Iter: 60 overflow: 0.994164 HPWL: 1560096761
|
||||
[NesterovSolve] Iter: 70 overflow: 0.994165 HPWL: 1554774586
|
||||
[NesterovSolve] Iter: 80 overflow: 0.994077 HPWL: 1558468307
|
||||
[NesterovSolve] Iter: 90 overflow: 0.994026 HPWL: 1561990551
|
||||
[NesterovSolve] Iter: 100 overflow: 0.993999 HPWL: 1562744741
|
||||
[NesterovSolve] Iter: 110 overflow: 0.993947 HPWL: 1563230947
|
||||
[NesterovSolve] Iter: 120 overflow: 0.993911 HPWL: 1565136404
|
||||
[NesterovSolve] Iter: 130 overflow: 0.993867 HPWL: 1569193928
|
||||
[NesterovSolve] Iter: 140 overflow: 0.993766 HPWL: 1575346564
|
||||
[NesterovSolve] Iter: 150 overflow: 0.993732 HPWL: 1583978189
|
||||
[NesterovSolve] Iter: 160 overflow: 0.993706 HPWL: 1596952209
|
||||
[NesterovSolve] Iter: 170 overflow: 0.993623 HPWL: 1618765427
|
||||
[NesterovSolve] Iter: 180 overflow: 0.993535 HPWL: 1657890635
|
||||
[NesterovSolve] Iter: 190 overflow: 0.993433 HPWL: 1728669762
|
||||
[NesterovSolve] Iter: 200 overflow: 0.993256 HPWL: 1831684995
|
||||
[NesterovSolve] Iter: 210 overflow: 0.992831 HPWL: 1955699898
|
||||
[NesterovSolve] Iter: 220 overflow: 0.992243 HPWL: 2103550626
|
||||
[NesterovSolve] Iter: 230 overflow: 0.991216 HPWL: 2275006532
|
||||
[NesterovSolve] Iter: 240 overflow: 0.989654 HPWL: 2468206176
|
||||
[NesterovSolve] Iter: 250 overflow: 0.987157 HPWL: 2696734652
|
||||
[NesterovSolve] Iter: 260 overflow: 0.983796 HPWL: 2981765708
|
||||
[NesterovSolve] Iter: 270 overflow: 0.979336 HPWL: 3352239567
|
||||
[NesterovSolve] Iter: 280 overflow: 0.974187 HPWL: 3837780564
|
||||
[NesterovSolve] Iter: 290 overflow: 0.966888 HPWL: 4455758135
|
||||
[NesterovSolve] Iter: 300 overflow: 0.956534 HPWL: 5179118538
|
||||
[NesterovSolve] Iter: 310 overflow: 0.944754 HPWL: 5975524701
|
||||
[NesterovSolve] Iter: 320 overflow: 0.931769 HPWL: 6792159301
|
||||
[NesterovSolve] Iter: 330 overflow: 0.918041 HPWL: 7563895725
|
||||
[NesterovSolve] Iter: 340 overflow: 0.900089 HPWL: 8247237488
|
||||
[NesterovSolve] Iter: 350 overflow: 0.874767 HPWL: 8833027362
|
||||
[NesterovSolve] Iter: 360 overflow: 0.84496 HPWL: 9262026725
|
||||
[NesterovSolve] Iter: 370 overflow: 0.816831 HPWL: 9723087585
|
||||
[NesterovSolve] Iter: 380 overflow: 0.780891 HPWL: 10351166790
|
||||
[NesterovSolve] Iter: 390 overflow: 0.748237 HPWL: 11018587998
|
||||
[NesterovSolve] Iter: 400 overflow: 0.713132 HPWL: 12227258975
|
||||
[NesterovSolve] Iter: 410 overflow: 0.672395 HPWL: 13183941296
|
||||
[NesterovSolve] Iter: 420 overflow: 0.631086 HPWL: 14313278736
|
||||
[NesterovSolve] Snapshot saved at iter = 427
|
||||
[NesterovSolve] Iter: 430 overflow: 0.591573 HPWL: 14525530958
|
||||
[NesterovSolve] Iter: 440 overflow: 0.546674 HPWL: 13604641697
|
||||
[NesterovSolve] Iter: 450 overflow: 0.50002 HPWL: 12942487503
|
||||
[NesterovSolve] Iter: 460 overflow: 0.465658 HPWL: 12530988216
|
||||
[NesterovSolve] Iter: 470 overflow: 0.438527 HPWL: 12363362542
|
||||
[NesterovSolve] Iter: 480 overflow: 0.411598 HPWL: 11792184906
|
||||
[NesterovSolve] Iter: 490 overflow: 0.383516 HPWL: 11313374722
|
||||
[NesterovSolve] Iter: 500 overflow: 0.356781 HPWL: 10882419956
|
||||
[NesterovSolve] Iter: 510 overflow: 0.332606 HPWL: 10483405942
|
||||
[NesterovSolve] Iter: 520 overflow: 0.311508 HPWL: 10139151789
|
||||
[NesterovSolve] Iter: 530 overflow: 0.289899 HPWL: 9861174515
|
||||
[NesterovSolve] Iter: 540 overflow: 0.262002 HPWL: 9659416789
|
||||
[NesterovSolve] Iter: 550 overflow: 0.222746 HPWL: 9502611747
|
||||
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
|
||||
[INFO GRT-0020] Min routing layer: met1
|
||||
[INFO GRT-0021] Max routing layer: met5
|
||||
[INFO GRT-0022] Global adjustment: 0%
|
||||
[INFO GRT-0023] Grid origin: (0, 0)
|
||||
[WARNING GRT-0043] No OR_DEFAULT vias defined.
|
||||
[INFO GRT-0224] Chose via L1M1_PR as default.
|
||||
[INFO GRT-0224] Chose via M1M2_PR as default.
|
||||
[INFO GRT-0224] Chose via M2M3_PR as default.
|
||||
[INFO GRT-0224] Chose via M3M4_PR as default.
|
||||
[INFO GRT-0224] Chose via M4M5_PR as default.
|
||||
[INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400
|
||||
[INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400
|
||||
[INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500
|
||||
[INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150
|
||||
[INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400
|
||||
[INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100
|
||||
[INFO GRT-0003] Macros: 0
|
||||
[INFO GRT-0004] Blockages: 1992109
|
||||
[INFO GRT-0019] Found 18045 clock nets.
|
||||
[INFO GRT-0001] Minimum degree: 2
|
||||
[INFO GRT-0002] Maximum degree: 68060
|
||||
[INFO GRT-0017] Processing 3406482 blockages on layer met1.
|
||||
[INFO GRT-0017] Processing 352 blockages on layer met4.
|
||||
[INFO GRT-0017] Processing 306 blockages on layer met5.
|
||||
|
||||
[INFO GRT-0053] Routing resources analysis:
|
||||
Routing Original Derated Resource
|
||||
Layer Direction Resources Resources Reduction (%)
|
||||
---------------------------------------------------------------
|
||||
li1 Vertical 0 0 0.00%
|
||||
met1 Horizontal 10045020 4932528 50.90%
|
||||
met2 Vertical 7533765 4522140 39.98%
|
||||
met3 Horizontal 5022510 3018528 39.90%
|
||||
met4 Vertical 3013506 1510488 49.88%
|
||||
met5 Horizontal 1004502 502336 49.99%
|
||||
---------------------------------------------------------------
|
||||
|
||||
[INFO GRT-0104] Minimal overflow 1142 occurring at round 0.
|
||||
[INFO GRT-0111] Final number of vias: 1822747
|
||||
[INFO GRT-0112] Final usage 3D: 8509419
|
||||
[WARNING GRT-0115] Global routing finished with overflow.
|
||||
|
||||
[INFO GRT-0096] Final congestion report:
|
||||
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
|
||||
---------------------------------------------------------------------------------------
|
||||
li1 0 48 0.00% 0 / 2 / 48
|
||||
met1 4932528 1296824 26.29% 4 / 0 / 37
|
||||
met2 4522140 1313654 29.05% 0 / 5 / 833
|
||||
met3 3018528 265850 8.81% 2 / 0 / 5
|
||||
met4 1510488 162384 10.75% 0 / 3 / 219
|
||||
met5 502336 2418 0.48% 0 / 0 / 0
|
||||
---------------------------------------------------------------------------------------
|
||||
Total 14486020 3041178 20.99% 6 / 10 / 1142
|
||||
|
||||
[INFO GRT-0018] Total wirelength: 28766879 um
|
||||
[INFO GPL-0036] TileLxLy: 0 0
|
||||
[INFO GPL-0037] TileSize: 6900 6900
|
||||
[INFO GPL-0038] TileCnt: 753 668
|
||||
[INFO GPL-0039] numRoutingLayers: 6
|
||||
[INFO GPL-0040] NumTiles: 503004
|
||||
[INFO GPL-0063] TotalRouteOverflowH2: 0.6000000238418579
|
||||
[INFO GPL-0064] TotalRouteOverflowV2: 92.03334939479828
|
||||
[INFO GPL-0065] OverflowTileCnt2: 803
|
||||
[INFO GPL-0066] 0.5%RC: 1.0183735974036332
|
||||
[INFO GPL-0067] 1.0%RC: 1.0091877158225815
|
||||
[INFO GPL-0068] 2.0%RC: 1.0045938579112907
|
||||
[INFO GPL-0069] 5.0%RC: 0.9496705569002577
|
||||
[INFO GPL-0070] 0.5rcK: 1.0
|
||||
[INFO GPL-0071] 1.0rcK: 1.0
|
||||
[INFO GPL-0072] 2.0rcK: 0.0
|
||||
[INFO GPL-0073] 5.0rcK: 0.0
|
||||
[INFO GPL-0074] FinalRC: 1.0137807
|
||||
[NesterovSolve] Iter: 560 overflow: 0.187525 HPWL: 9358515093
|
||||
[NesterovSolve] Iter: 570 overflow: 0.161221 HPWL: 9283610515
|
||||
[NesterovSolve] Iter: 580 overflow: 0.140208 HPWL: 9193050204
|
||||
[NesterovSolve] Iter: 590 overflow: 0.123307 HPWL: 9083231317
|
||||
[NesterovSolve] Iter: 600 overflow: 0.109013 HPWL: 9066029377
|
||||
[NesterovSolve] Finished with Overflow: 0.099666
|
||||
|
||||
==========================================================================
|
||||
global place report_checks -path_delay min
|
||||
--------------------------------------------------------------------------
|
||||
Startpoint: externalResetVector[1] (input port clocked by clk)
|
||||
Endpoint: _404211_ (removal check against rising-edge clock clk)
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 0.00 v externalResetVector[1] (in)
|
||||
2 0.22 externalResetVector[1] (net)
|
||||
0.23 0.11 0.11 v _346224_/B (sky130_fd_sc_hd__nand2_1)
|
||||
0.09 0.14 0.26 ^ _346224_/Y (sky130_fd_sc_hd__nand2_1)
|
||||
1 0.00 _000305_ (net)
|
||||
0.09 0.00 0.26 ^ _404211_/SET_B (sky130_fd_sc_hd__dfbbp_1)
|
||||
0.26 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ _404211_/CLK (sky130_fd_sc_hd__dfbbp_1)
|
||||
0.10 0.10 library removal time
|
||||
0.10 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
0.10 data required time
|
||||
-0.26 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.16 slack (MET)
|
||||
|
||||
|
||||
Startpoint: iBusWB_DAT_MISO[8] (input port clocked by clk)
|
||||
Endpoint: _348151_ (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[8] (in)
|
||||
1 0.03 iBusWB_DAT_MISO[8] (net)
|
||||
0.00 0.00 0.00 ^ _348151_/D (sky130_fd_sc_hd__dfxtp_1)
|
||||
0.00 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ _348151_/CLK (sky130_fd_sc_hd__dfxtp_1)
|
||||
-0.03 -0.03 library hold time
|
||||
-0.03 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
-0.03 data required time
|
||||
-0.00 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.03 slack (MET)
|
||||
|
||||
|
||||
|
||||
==========================================================================
|
||||
global place report_checks -path_delay max
|
||||
--------------------------------------------------------------------------
|
||||
Startpoint: externalResetVector[27] (input port clocked by clk)
|
||||
Endpoint: _404237_ (recovery check against rising-edge clock clk)
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 0.00 v externalResetVector[27] (in)
|
||||
2 0.76 externalResetVector[27] (net)
|
||||
2.67 1.34 1.34 v _346252_/B (sky130_fd_sc_hd__nand2_1)
|
||||
0.47 0.60 1.94 ^ _346252_/Y (sky130_fd_sc_hd__nand2_1)
|
||||
1 0.00 _000357_ (net)
|
||||
0.47 0.00 1.94 ^ _404237_/SET_B (sky130_fd_sc_hd__dfbbp_1)
|
||||
1.94 data arrival time
|
||||
|
||||
0.00 40.00 40.00 clock clk (rise edge)
|
||||
0.00 40.00 clock network delay (ideal)
|
||||
0.00 40.00 clock reconvergence pessimism
|
||||
40.00 ^ _404237_/CLK (sky130_fd_sc_hd__dfbbp_1)
|
||||
-0.07 39.93 library recovery time
|
||||
39.93 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.93 data required time
|
||||
-1.94 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
37.99 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _404560_ (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
|
||||
(rising clock gating-check end-point clocked by clk')
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ _404560_/CLK (sky130_fd_sc_hd__dfrtp_1)
|
||||
7.05 4.15 4.15 ^ _404560_/Q (sky130_fd_sc_hd__dfrtp_1)
|
||||
7 0.83 dBusWB_CYC (net)
|
||||
7.05 0.00 4.15 ^ _176631_/A2 (sky130_fd_sc_hd__a31oi_1)
|
||||
0.87 0.54 4.69 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
|
||||
2 0.01 _057182_ (net)
|
||||
0.87 0.00 4.69 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
|
||||
59.18 43.79 48.48 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
|
||||
365 2.05 _057233_ (net)
|
||||
59.18 0.11 48.59 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
|
||||
43.23 45.63 94.22 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
|
||||
42 0.22 _057237_ (net)
|
||||
43.23 0.01 94.23 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
|
||||
0.71 11.09 105.31 v _176698_/X (sky130_fd_sc_hd__a22o_1)
|
||||
2 0.01 _057243_ (net)
|
||||
0.71 0.00 105.31 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
|
||||
1895.01 1381.65 1486.96 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
|
||||
9416 65.04 _057333_ (net)
|
||||
1895.02 3.84 1490.81 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
|
||||
32.87 25946.33 27437.13 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
|
||||
1024 4.59 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
|
||||
32.87 3.59 27440.72 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
|
||||
0.88 12.98 27453.70 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
|
||||
8 0.10 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
|
||||
0.88 0.01 27453.71 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
|
||||
0.85 0.40 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
|
||||
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
|
||||
0.85 0.00 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
|
||||
27454.11 data arrival time
|
||||
|
||||
0.00 20.00 20.00 clock clk' (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
|
||||
-0.35 19.65 library setup time
|
||||
19.65 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
19.65 data required time
|
||||
-27454.11 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
-27434.46 slack (VIOLATED)
|
||||
|
||||
|
||||
|
||||
==========================================================================
|
||||
global place report_checks -unconstrained
|
||||
--------------------------------------------------------------------------
|
||||
Startpoint: externalResetVector[27] (input port clocked by clk)
|
||||
Endpoint: _404237_ (recovery check against rising-edge clock clk)
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 0.00 v externalResetVector[27] (in)
|
||||
2 0.76 externalResetVector[27] (net)
|
||||
2.67 1.34 1.34 v _346252_/B (sky130_fd_sc_hd__nand2_1)
|
||||
0.47 0.60 1.94 ^ _346252_/Y (sky130_fd_sc_hd__nand2_1)
|
||||
1 0.00 _000357_ (net)
|
||||
0.47 0.00 1.94 ^ _404237_/SET_B (sky130_fd_sc_hd__dfbbp_1)
|
||||
1.94 data arrival time
|
||||
|
||||
0.00 40.00 40.00 clock clk (rise edge)
|
||||
0.00 40.00 clock network delay (ideal)
|
||||
0.00 40.00 clock reconvergence pessimism
|
||||
40.00 ^ _404237_/CLK (sky130_fd_sc_hd__dfbbp_1)
|
||||
-0.07 39.93 library recovery time
|
||||
39.93 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.93 data required time
|
||||
-1.94 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
37.99 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _404560_ (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
|
||||
(rising clock gating-check end-point clocked by clk')
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ _404560_/CLK (sky130_fd_sc_hd__dfrtp_1)
|
||||
7.05 4.15 4.15 ^ _404560_/Q (sky130_fd_sc_hd__dfrtp_1)
|
||||
7 0.83 dBusWB_CYC (net)
|
||||
7.05 0.00 4.15 ^ _176631_/A2 (sky130_fd_sc_hd__a31oi_1)
|
||||
0.87 0.54 4.69 v _176631_/Y (sky130_fd_sc_hd__a31oi_1)
|
||||
2 0.01 _057182_ (net)
|
||||
0.87 0.00 4.69 v _176688_/A2 (sky130_fd_sc_hd__a211oi_1)
|
||||
59.18 43.79 48.48 ^ _176688_/Y (sky130_fd_sc_hd__a211oi_1)
|
||||
365 2.05 _057233_ (net)
|
||||
59.18 0.11 48.59 ^ _176692_/A (sky130_fd_sc_hd__nor3_1)
|
||||
43.23 45.63 94.22 v _176692_/Y (sky130_fd_sc_hd__nor3_1)
|
||||
42 0.22 _057237_ (net)
|
||||
43.23 0.01 94.23 v _176698_/A2 (sky130_fd_sc_hd__a22o_1)
|
||||
0.71 11.09 105.31 v _176698_/X (sky130_fd_sc_hd__a22o_1)
|
||||
2 0.01 _057243_ (net)
|
||||
0.71 0.00 105.31 v _176788_/A2 (sky130_fd_sc_hd__o32ai_1)
|
||||
1895.01 1381.65 1486.96 ^ _176788_/Y (sky130_fd_sc_hd__o32ai_1)
|
||||
9416 65.04 _057333_ (net)
|
||||
1895.02 3.84 1490.81 ^ _176798_/A2 (sky130_fd_sc_hd__o21ai_0)
|
||||
32.87 25946.33 27437.13 v _176798_/Y (sky130_fd_sc_hd__o21ai_0)
|
||||
1024 4.59 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
|
||||
32.87 3.59 27440.72 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
|
||||
0.88 12.98 27453.70 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
|
||||
8 0.10 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
|
||||
0.88 0.01 27453.71 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
|
||||
0.85 0.40 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
|
||||
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
|
||||
0.85 0.00 27454.11 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
|
||||
27454.11 data arrival time
|
||||
|
||||
0.00 20.00 20.00 clock clk' (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
|
||||
-0.35 19.65 library setup time
|
||||
19.65 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
19.65 data required time
|
||||
-27454.11 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
-27434.46 slack (VIOLATED)
|
||||
|
||||
|
||||
|
||||
==========================================================================
|
||||
global place report_tns
|
||||
--------------------------------------------------------------------------
|
||||
tns -64188920.00
|
||||
|
||||
==========================================================================
|
||||
global place report_wns
|
||||
--------------------------------------------------------------------------
|
||||
wns -27434.46
|
||||
|
||||
==========================================================================
|
||||
global place report_worst_slack
|
||||
--------------------------------------------------------------------------
|
||||
worst slack -27434.46
|
||||
|
||||
==========================================================================
|
||||
global place report_clock_skew
|
||||
--------------------------------------------------------------------------
|
||||
Clock clk
|
||||
Latency CRPR Skew
|
||||
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].genblk1.STORAGE/GATE ^
|
||||
0.26
|
||||
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.Do0_FF[6]/CLK ^
|
||||
0.00 0.00 0.26
|
||||
|
||||
|
||||
==========================================================================
|
||||
global place report_power
|
||||
--------------------------------------------------------------------------
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.06e-01 5.37e-03 9.29e-07 1.12e-01 11.4%
|
||||
Combinational 7.55e-01 1.12e-01 8.90e-07 8.66e-01 88.6%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 8.61e-01 1.17e-01 1.82e-06 9.78e-01 100.0%
|
||||
88.0% 12.0% 0.0%
|
||||
|
||||
==========================================================================
|
||||
global place report_design_area
|
||||
--------------------------------------------------------------------------
|
||||
Design area 4959944 u^2 25% utilization.
|
||||
|
||||
Elapsed time: 12:51.27[h:]min:sec. CPU time: user 759.70 sys 11.43 (99%). Peak memory: 15006996KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,39 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0094] Created 400000 Insts
|
||||
[INFO ODB-0094] Created 500000 Insts
|
||||
[INFO ODB-0094] Created 600000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 663999 components and 2644247 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 1327998 connections.
|
||||
[INFO ODB-0133] Created 327254 nets and 1315959 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
|
||||
Found 0 macro blocks.
|
||||
Using 1u default distance from corners.
|
||||
Using 2 tracks default min distance between IO pins.
|
||||
[INFO PPL-0010] Tentative 0 to set up sections.
|
||||
[INFO PPL-0001] Number of slots 18082
|
||||
[INFO PPL-0002] Number of I/O 254
|
||||
[INFO PPL-0003] Number of I/O w/sink 254
|
||||
[INFO PPL-0004] Number of I/O w/o sink 7
|
||||
[INFO PPL-0005] Slots per section 200
|
||||
[INFO PPL-0006] Slots increase factor 0.01
|
||||
[INFO PPL-0008] Successfully assigned pins to sections.
|
||||
[INFO PPL-0012] I/O nets HPWL: 308203.00 um.
|
||||
Elapsed time: 0:11.71[h:]min:sec. CPU time: user 11.15 sys 0.52 (99%). Peak memory: 1549800KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
@ -0,0 +1,29 @@
|
||||
OpenROAD v2.0-1901-g6157d4945
|
||||
This program is licensed under the BSD-3 license. See the LICENSE file for details.
|
||||
Components of this program may be licensed under more restrictive licenses which must be honored.
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0223] Created 11 technology layers
|
||||
[INFO ODB-0224] Created 25 technology vias
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
|
||||
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0225] Created 437 library cells
|
||||
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
|
||||
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
|
||||
[INFO ODB-0128] Design: A2P_WB
|
||||
[INFO ODB-0094] Created 100000 Insts
|
||||
[INFO ODB-0094] Created 200000 Insts
|
||||
[INFO ODB-0094] Created 300000 Insts
|
||||
[INFO ODB-0094] Created 400000 Insts
|
||||
[INFO ODB-0094] Created 500000 Insts
|
||||
[INFO ODB-0094] Created 600000 Insts
|
||||
[INFO ODB-0094] Created 700000 Insts
|
||||
[INFO ODB-0097] Created 100000 Nets
|
||||
[INFO ODB-0097] Created 200000 Nets
|
||||
[INFO ODB-0097] Created 300000 Nets
|
||||
[INFO ODB-0130] Created 254 pins.
|
||||
[INFO ODB-0131] Created 715330 components and 2849571 component-terminals.
|
||||
[INFO ODB-0132] Created 2 special nets and 1430660 connections.
|
||||
[INFO ODB-0133] Created 378585 nets and 1412715 connections.
|
||||
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
|
||||
[INFO DPL-0001] Placed 1982253 filler instances.
|
||||
Elapsed time: 0:20.97[h:]min:sec. CPU time: user 19.56 sys 1.05 (98%). Peak memory: 2436392KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,4 @@
|
||||
{
|
||||
"drt::wire length::total" : 22781418
|
||||
, "drt::vias::total" : 3240309
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,42 @@
|
||||
[INFO] Reporting cells prior to loading DEF ...
|
||||
[INFO] Reading DEF ...
|
||||
[INFO] Clearing cells...
|
||||
[INFO] ... preserving 'VIA_L1M1_PR'
|
||||
[INFO] ... preserving 'VIA_L1M1_PR_R'
|
||||
[INFO] ... preserving 'VIA_L1M1_PR_M'
|
||||
[INFO] ... preserving 'VIA_L1M1_PR_MR'
|
||||
[INFO] ... preserving 'VIA_L1M1_PR_C'
|
||||
[INFO] ... preserving 'VIA_M1M2_PR'
|
||||
[INFO] ... preserving 'VIA_M1M2_PR_R'
|
||||
[INFO] ... preserving 'VIA_M1M2_PR_M'
|
||||
[INFO] ... preserving 'VIA_M1M2_PR_MR'
|
||||
[INFO] ... preserving 'VIA_M1M2_PR_C'
|
||||
[INFO] ... preserving 'VIA_M2M3_PR'
|
||||
[INFO] ... preserving 'VIA_M2M3_PR_R'
|
||||
[INFO] ... preserving 'VIA_M2M3_PR_M'
|
||||
[INFO] ... preserving 'VIA_M2M3_PR_MR'
|
||||
[INFO] ... preserving 'VIA_M2M3_PR_C'
|
||||
[INFO] ... preserving 'VIA_M3M4_PR'
|
||||
[INFO] ... preserving 'VIA_M3M4_PR_R'
|
||||
[INFO] ... preserving 'VIA_M3M4_PR_M'
|
||||
[INFO] ... preserving 'VIA_M3M4_PR_MR'
|
||||
[INFO] ... preserving 'VIA_M3M4_PR_C'
|
||||
[INFO] ... preserving 'VIA_M4M5_PR'
|
||||
[INFO] ... preserving 'VIA_M4M5_PR_R'
|
||||
[INFO] ... preserving 'VIA_M4M5_PR_M'
|
||||
[INFO] ... preserving 'VIA_M4M5_PR_MR'
|
||||
[INFO] ... preserving 'VIA_M4M5_PR_C'
|
||||
[INFO] ... preserving 'VIA_via_1600x480'
|
||||
[INFO] ... preserving 'VIA_via2_1600x480'
|
||||
[INFO] ... preserving 'VIA_via3_1600x480'
|
||||
[INFO] ... preserving 'VIA_via4_1600x1600'
|
||||
[INFO] Merging GDS/OAS files...
|
||||
./platforms/sky130hd/gds/sky130_fd_sc_hd.gds
|
||||
[INFO] Copying toplevel cell 'A2P_WB'
|
||||
INFO: Reading config file: ./platforms/sky130hd/fill.json
|
||||
[INFO] Checking for missing cell from GDS/OAS...
|
||||
[INFO] All LEF cells have matching GDS/OAS cells
|
||||
[INFO] Checking for orphan cell in the final layout...
|
||||
[INFO] No orphan cells
|
||||
[INFO] Writing out GDS/OAS 'results/sky130hd/a2p/base/6_1_merged.gds'
|
||||
Elapsed time: 0:54.67[h:]min:sec. CPU time: user 51.48 sys 2.67 (99%). Peak memory: 6583756KB.
|
||||
@ -0,0 +1,2 @@
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,4 @@
|
||||
Warning - class CORE ANTENNACELL is not found. This message can be ignored if not in the antenna-avoid flow
|
||||
Number of pins violated: 0
|
||||
Number of nets violated: 0
|
||||
Total number of unspecial nets: 378585
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 2.5 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 2.1 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.8 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.9 MiB |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,146 @@
|
||||
|
||||
29. Printing statistics.
|
||||
|
||||
=== A2P_WB ===
|
||||
|
||||
Number of wires: 361279
|
||||
Number of wire bits: 361504
|
||||
Number of public wires: 185361
|
||||
Number of public wire bits: 185586
|
||||
Number of memories: 0
|
||||
Number of memory bits: 0
|
||||
Number of processes: 0
|
||||
Number of cells: 432348
|
||||
sky130_fd_sc_hd__a2111o_1 2
|
||||
sky130_fd_sc_hd__a2111oi_0 839
|
||||
sky130_fd_sc_hd__a2111oi_2 1
|
||||
sky130_fd_sc_hd__a211o_1 73
|
||||
sky130_fd_sc_hd__a211o_2 1
|
||||
sky130_fd_sc_hd__a211oi_1 228
|
||||
sky130_fd_sc_hd__a21boi_0 29
|
||||
sky130_fd_sc_hd__a21boi_1 1
|
||||
sky130_fd_sc_hd__a21o_1 167
|
||||
sky130_fd_sc_hd__a21oi_1 6354
|
||||
sky130_fd_sc_hd__a221o_1 46
|
||||
sky130_fd_sc_hd__a221o_2 1
|
||||
sky130_fd_sc_hd__a221oi_1 460
|
||||
sky130_fd_sc_hd__a222oi_1 93
|
||||
sky130_fd_sc_hd__a22o_1 122
|
||||
sky130_fd_sc_hd__a22oi_1 381
|
||||
sky130_fd_sc_hd__a2bb2oi_1 5
|
||||
sky130_fd_sc_hd__a311o_1 51
|
||||
sky130_fd_sc_hd__a311oi_1 3990
|
||||
sky130_fd_sc_hd__a31o_2 19
|
||||
sky130_fd_sc_hd__a31oi_1 2241
|
||||
sky130_fd_sc_hd__a32o_1 146
|
||||
sky130_fd_sc_hd__a32oi_1 405
|
||||
sky130_fd_sc_hd__a41o_1 5
|
||||
sky130_fd_sc_hd__a41oi_1 24
|
||||
sky130_fd_sc_hd__and2_0 6
|
||||
sky130_fd_sc_hd__and2_1 9078
|
||||
sky130_fd_sc_hd__and2_2 2
|
||||
sky130_fd_sc_hd__and2b_2 2
|
||||
sky130_fd_sc_hd__and3_1 2682
|
||||
sky130_fd_sc_hd__and3_2 94
|
||||
sky130_fd_sc_hd__and3_4 3
|
||||
sky130_fd_sc_hd__and3b_1 6
|
||||
sky130_fd_sc_hd__and3b_2 188
|
||||
sky130_fd_sc_hd__and3b_4 6
|
||||
sky130_fd_sc_hd__and4_1 9
|
||||
sky130_fd_sc_hd__and4_2 300
|
||||
sky130_fd_sc_hd__and4b_1 1
|
||||
sky130_fd_sc_hd__and4b_2 900
|
||||
sky130_fd_sc_hd__and4bb_2 900
|
||||
sky130_fd_sc_hd__buf_1 3103
|
||||
sky130_fd_sc_hd__buf_2 579
|
||||
sky130_fd_sc_hd__buf_4 103
|
||||
sky130_fd_sc_hd__buf_6 5
|
||||
sky130_fd_sc_hd__clkbuf_1 21240
|
||||
sky130_fd_sc_hd__clkbuf_16 2844
|
||||
sky130_fd_sc_hd__clkbuf_2 6400
|
||||
sky130_fd_sc_hd__clkbuf_4 20
|
||||
sky130_fd_sc_hd__clkinv_1 17
|
||||
sky130_fd_sc_hd__conb_1 290
|
||||
sky130_fd_sc_hd__dfbbp_1 31
|
||||
sky130_fd_sc_hd__dfrtp_1 251
|
||||
sky130_fd_sc_hd__dfstp_2 3
|
||||
sky130_fd_sc_hd__dfxtp_1 59682
|
||||
sky130_fd_sc_hd__dlclkp_1 9084
|
||||
sky130_fd_sc_hd__dlxtp_1 71168
|
||||
sky130_fd_sc_hd__ebufn_2 75440
|
||||
sky130_fd_sc_hd__fa_1 1118
|
||||
sky130_fd_sc_hd__ha_1 1053
|
||||
sky130_fd_sc_hd__inv_1 19439
|
||||
sky130_fd_sc_hd__inv_2 8
|
||||
sky130_fd_sc_hd__inv_4 256
|
||||
sky130_fd_sc_hd__maj3_1 15
|
||||
sky130_fd_sc_hd__mux2_1 74
|
||||
sky130_fd_sc_hd__mux2_2 52601
|
||||
sky130_fd_sc_hd__mux2_4 1
|
||||
sky130_fd_sc_hd__mux2i_1 4048
|
||||
sky130_fd_sc_hd__mux4_1 684
|
||||
sky130_fd_sc_hd__mux4_2 2835
|
||||
sky130_fd_sc_hd__nand2_1 41766
|
||||
sky130_fd_sc_hd__nand2_2 2
|
||||
sky130_fd_sc_hd__nand2_4 1
|
||||
sky130_fd_sc_hd__nand2b_1 90
|
||||
sky130_fd_sc_hd__nand3_1 13759
|
||||
sky130_fd_sc_hd__nand3_2 1
|
||||
sky130_fd_sc_hd__nand3b_1 15
|
||||
sky130_fd_sc_hd__nand4_1 386
|
||||
sky130_fd_sc_hd__nand4b_1 9
|
||||
sky130_fd_sc_hd__nor2_1 4831
|
||||
sky130_fd_sc_hd__nor2b_1 80
|
||||
sky130_fd_sc_hd__nor3_1 931
|
||||
sky130_fd_sc_hd__nor3b_1 32
|
||||
sky130_fd_sc_hd__nor3b_2 94
|
||||
sky130_fd_sc_hd__nor3b_4 3
|
||||
sky130_fd_sc_hd__nor4_1 241
|
||||
sky130_fd_sc_hd__nor4_2 2
|
||||
sky130_fd_sc_hd__nor4b_1 32
|
||||
sky130_fd_sc_hd__nor4b_2 301
|
||||
sky130_fd_sc_hd__nor4bb_1 2
|
||||
sky130_fd_sc_hd__o2111ai_1 463
|
||||
sky130_fd_sc_hd__o211a_1 7
|
||||
sky130_fd_sc_hd__o211ai_1 312
|
||||
sky130_fd_sc_hd__o211ai_2 1
|
||||
sky130_fd_sc_hd__o21a_1 63
|
||||
sky130_fd_sc_hd__o21ai_0 3062
|
||||
sky130_fd_sc_hd__o21ai_1 28
|
||||
sky130_fd_sc_hd__o21ba_2 1
|
||||
sky130_fd_sc_hd__o21bai_1 15
|
||||
sky130_fd_sc_hd__o221a_1 1
|
||||
sky130_fd_sc_hd__o221a_2 4
|
||||
sky130_fd_sc_hd__o221ai_1 1333
|
||||
sky130_fd_sc_hd__o22a_1 28
|
||||
sky130_fd_sc_hd__o22ai_1 520
|
||||
sky130_fd_sc_hd__o2bb2ai_1 8
|
||||
sky130_fd_sc_hd__o311a_1 31
|
||||
sky130_fd_sc_hd__o311ai_0 247
|
||||
sky130_fd_sc_hd__o31a_1 13
|
||||
sky130_fd_sc_hd__o31ai_1 108
|
||||
sky130_fd_sc_hd__o31ai_2 3
|
||||
sky130_fd_sc_hd__o32a_1 23
|
||||
sky130_fd_sc_hd__o32ai_1 206
|
||||
sky130_fd_sc_hd__o32ai_4 1
|
||||
sky130_fd_sc_hd__o41a_1 1
|
||||
sky130_fd_sc_hd__o41ai_1 115
|
||||
sky130_fd_sc_hd__o41ai_2 1
|
||||
sky130_fd_sc_hd__or2_1 3
|
||||
sky130_fd_sc_hd__or2_2 43
|
||||
sky130_fd_sc_hd__or3_1 68
|
||||
sky130_fd_sc_hd__or3b_2 3
|
||||
sky130_fd_sc_hd__or4_1 31
|
||||
sky130_fd_sc_hd__or4b_2 4
|
||||
sky130_fd_sc_hd__or4b_4 1
|
||||
sky130_fd_sc_hd__xnor2_1 539
|
||||
sky130_fd_sc_hd__xnor2_2 7
|
||||
sky130_fd_sc_hd__xnor2_4 1
|
||||
sky130_fd_sc_hd__xnor3_1 10
|
||||
sky130_fd_sc_hd__xnor3_2 3
|
||||
sky130_fd_sc_hd__xor2_1 205
|
||||
sky130_fd_sc_hd__xor2_2 2
|
||||
sky130_fd_sc_hd__xor3_1 2
|
||||
|
||||
Chip area for module '\A2P_WB': 4825367.910407
|
||||
|
||||
Loading…
Reference in New Issue