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try sky130

master
wtf 1 year ago
parent
commit
bd95f8c190
  1. 53
      build/openroad/config.mk
  2. 24
      build/openroad/constraint.sdc
  3. 44
      build/openroad/readme.md
  4. 1
      build/openroad/src/A2P_WB.v

53
build/openroad/config.mk

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# design and tech
export DESIGN_NICKNAME = a2p
export DESIGN_NAME = A2P_WB
export PLATFORM = sky130hd

export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

$(info Source files:)
$(info $(VERILOG_FILES))
$(info ..................................................)

# design and tech
unit = a2p

# 5% utilization
#[INFO PDN-0013] Inserting stdcell grid - grid
#Command terminated by signal 9
#export DIE_AREA = 0 0 10000 10000
#export CORE_AREA = 100 100 10000 10000
# 21% utilization
#Error: resize.tcl, 88 invalid command name "sta::max_slew_violation_count"
export DIE_AREA = 0 0 5000 5000
export CORE_AREA = 100 100 5000 5000

#export CORE_UTILIZATION = 100
#export CORE_ASPECT_RATIO = 1
#export CORE_MARGIN = 2

# a2o fu stuff
# keeps hierarchy of some cells even if flattening
#export PRESERVE_CELLS ?= tri_144x78_2r4w
# no flatten
#export SYNTH_NO_FLAT ?= 1
# don't optimize tri_144x78_2r4w
#export SYNTH_OPT_SELECTION ?= fu

#export PLACE_DENSITY ?= 0.80
# also set cycle time in constraint.sdc! derive it there from this?
#export ABC_CLOCK_PERIOD_IN_PS ?= 10000
#export ABC_DEFAULT_SCRIPT ?= 1

# fanout doesn't get adjusted to fix paths? or resizer not working
export SYNTH_MAX_FANOUT ?= 32
export SYNTH_MAX_TRAN ?= 100

#wtf can't specify in resizer anymore?
#export RS_BUF_CELL ?= BUF_X4
#export RS_MAX_FO ?= 20

export REPORT_SLACK_MAX_PATHS ?= 100


24
build/openroad/constraint.sdc

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set clk_name clk
# make it easy
set clk_period 50.0

set input_delay_value 1
set output_delay_value 1

# define clock
set clkPort [get_ports $clk_name]
create_clock $clkPort -name clk -period $clk_period

# apply clock to ins and outs
set clk_index [lsearch [all_inputs] $clkPort]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]

# false paths
set_false_path -from [get_ports {reset}] -to [get_clocks clk]
#wtf - is this the dc write path?
set_false_path -from [get_nets {dBusWB_ACK}]
set_false_path -from [get_nets {a2p_wb/dbuswb_ack}]
set_false_path -from [get_nets {a2p_wb/dbuswb*}]

44
build/openroad/readme.md

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#### https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow

create dir and add sources

```
cd ../../..
make DESIGN_CONFIG=./designs/sky130hd/a2p/config.mk
```


## docs

https://openroad.readthedocs.io/en/latest/user/UserGuide.html#option-1-rtl-to-gds-flow

http://www.clifford.at/yosys/files/yosys_manual.pdf

https://people.eecs.berkeley.edu/~alanmi/abc/

https://github.com/The-OpenROAD-Project/OpenSTA/blob/35a3f1e4e3f148b30678f9455e64d220c6758462/doc/OpenSTA.pdf


### steps

1. initial synth/timing

* initialize floorplan (initialize_floorplan)
* gate_resizer (multiple commands)
* can set estimated wire rc per layer
* can add buffers on I/O
* repairs fanouts/caps/etc.
* STA can run before and/or after this
* OpenSTA (sta)

2. full PD

* macro place (macro_placement)
* tapcell/endcap (tapcell)
* global placement (global_placement)
* detailed placement (legalize_placement)
* CTS (clock_tree_synthesis)
* global routing (fast_route) ***the unit hangs appear here in report_power***
* detailed routing (detailed_route)

1
build/openroad/src/A2P_WB.v

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/home/wtf/projects/a2p/core/A2P_WB.v
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