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# A2P |
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<img align="right" src="media/banner.png"> |
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## Back to the 90s! |
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A2P is a mashup of OpenPOWER architecture and VexRiscv, creating a new 32b Power core for experimentation and lightweight designs. |
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## Status |
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### Function |
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<img align="right" width="50%" src="media/sim.png"> |
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* Ops (100+) not thoroughly tested, but running a minimal kernel and partial Litex BIOS in Verilator and on FPGAs. Likely still |
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some bugs in CR/XER handling. |
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* Need to define supported translation modes. |
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* SOC builds with Litex; software is built manually and runs from 'ROM' with on-board RAM. |
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* Core and SOC run in Verilator/pyverilator. SOC uses emulated host UART. |
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### FPGA Implementation |
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* Currently using Cmod A7-35T board. |
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* Needs SOC code update to access external SRAM. I2C works. |
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<img width="50%" src="media/fpga.png"> |
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* A lot of LUTs are being used by bypass/GPR write. Recent analysis (100MHz, Vivado/Artix): |
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``` |
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cellanal.py |
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--- cells_ff.txt --- |
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Total: 1791 |
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IC 115 |
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decode 244 |
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execute 456 |
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regfile 0 |
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hazards 38 |
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ALU2 32 |
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MULDIV 136 |
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memory 295 |
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DC 69 |
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SPR 239 |
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MSR 15 |
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writeBack 1 |
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ibus 32 |
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dbus 32 |
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SPINAL _zz_ 87 |
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Total in matched areas 1791 |
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*** >32 bits (93): a2p_i/A2P_WB/inst/IBusCachedPlugin_fetchPc_pcReg_reg *** |
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*** >32 bits (52): a2p_i/A2P_WB/inst/memory_to_writeBack_MUL_LOW_reg *** |
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Totals by cells: |
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1: 131 131 |
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2: 16 163 |
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3: 7 184 |
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4: 6 208 |
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5: 18 298 |
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6: 1 304 |
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7: 1 311 |
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8: 5 351 |
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10: 1 361 |
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11: 2 383 |
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26: 1 409 |
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30: 3 499 |
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31: 5 654 |
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32: 31 1646 |
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52: 1 1698 |
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93: 1 1791 |
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--- cells_lut.txt --- |
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Total: 2539 |
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IC 85 |
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decode 262 |
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execute 1758 |
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regfile 9 |
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hazards 35 |
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ALU2 0 |
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MULDIV 145 |
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memory 133 |
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DC 1 |
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SPR 56 |
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MSR 0 |
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writeBack 0 |
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ibus 1 |
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dbus 8 |
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SPINAL _zz_ 46 |
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Total in matched areas 2539 |
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*** >32 bits (35): a2p_i/A2P_WB/inst/Hazards_writeBackBuffer_payload_data *** |
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*** >32 bits (62): a2p_i/A2P_WB/inst/IBusCachedPlugin_fetchPc_pcReg_reg *** |
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*** >32 bits (34): a2p_i/A2P_WB/inst/MULDIV1_result *** |
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*** >32 bits (66): a2p_i/A2P_WB/inst/MULDIV_accumulator *** |
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*** >32 bits (40): a2p_i/A2P_WB/inst/_zz_141_ *** |
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*** >32 bits (42): a2p_i/A2P_WB/inst/decode_to_execute_RA *** |
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*** >32 bits (220): a2p_i/A2P_WB/inst/decode_to_execute_RB *** |
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*** >32 bits (107): a2p_i/A2P_WB/inst/execute_to_memory_BRANCH_CALC *** |
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*** >32 bits (64): a2p_i/A2P_WB/inst/execute_to_memory_CR_WRITE_imm *** |
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*** >32 bits (212): a2p_i/A2P_WB/inst/execute_to_memory_DECODER_stageables_49 *** |
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*** >32 bits (1028): a2p_i/A2P_WB/inst/execute_to_memory_REGFILE_WRITE_DATA *** |
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*** >32 bits (86): a2p_i/A2P_WB/inst/execute_to_memory_SRC_CR *** |
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*** >32 bits (37): a2p_i/A2P_WB/inst/execute_to_memory_XER_WRITE_imm *** |
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*** >32 bits (68): a2p_i/A2P_WB/inst/memory_to_writeBack_MUL_LOW *** |
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Totals by cells: |
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1: 158 158 |
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2: 1 160 |
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3: 5 175 |
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4: 1 179 |
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5: 5 204 |
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8: 2 220 |
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9: 1 229 |
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17: 1 246 |
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20: 2 286 |
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25: 1 311 |
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31: 1 342 |
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32: 3 438 |
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34: 1 472 |
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35: 1 507 |
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37: 1 544 |
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40: 1 584 |
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42: 1 626 |
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62: 1 688 |
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64: 1 752 |
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66: 1 818 |
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68: 1 886 |
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86: 1 972 |
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107: 1 1079 |
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212: 1 1291 |
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220: 1 1511 |
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1028: 1 2539 |
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``` |
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