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314 lines
9.5 KiB
Verilog
314 lines
9.5 KiB
Verilog
`include "defs.v"
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module top #(
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parameter [0:15] CORE_TYPES = {`CORE_TYPE_WB2, `CORE_TYPE_WB2, `CORE_TYPE_WB2, `CORE_TYPE_WB2},
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parameter [0:3] BUS_TYPE = `BUS_TYPE_WB2
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) (
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input clk,
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input rst,
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output wb_i_stb,
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output wb_i_cyc,
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output [31:0] wb_i_adr,
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input wb_i_ack,
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input [31:0] wb_i_datr,
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output wb_d_stb,
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output wb_d_cyc,
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output [31:0] wb_d_adr,
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output wb_d_we,
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output [3:0] wb_d_sel,
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output [31:0] wb_d_datw,
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input wb_d_ack,
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input [31:0] wb_d_datr
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);
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wire [`WB2_WB_IN_START:0] c0_in;
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wire [`WB2_WB_OUT_START:0] c0_out;
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wire [`WB2_WB_IN_START:0] c1_in;
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wire [`WB2_WB_OUT_START:0] c1_out;
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wire [`WB2_WB_IN_START:0] c2_in;
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wire [`WB2_WB_OUT_START:0] c2_out;
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wire [`WB2_WB_IN_START:0] c3_in;
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wire [`WB2_WB_OUT_START:0] c3_out;
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wire [`BUS_WB2_IN_START:0] wb_in;
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wire [`BUS_WB2_OUT_START:0] wb_out;
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wire rst_0 /*verilator public*/;
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wire wb_i_stb_0;
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wire wb_i_cyc_0;
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//wire wb_i_we_0;
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//wire [3:0] wb_i_sel_0;
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wire [31:2] wb_i_adr_0;
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//wire [31:0] wb_i_datw_0;
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wire wb_i_ack_0;
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wire [31:0] wb_i_datr_0;
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wire wb_d_stb_0;
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wire wb_d_cyc_0;
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wire wb_d_we_0;
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wire [3:0] wb_d_sel_0;
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wire [31:2] wb_d_adr_0;
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wire [31:0] wb_d_datw_0;
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wire wb_d_ack_0;
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wire [31:0] wb_d_datr_0;
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wire ext_int_0;
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wire ext_int_s_0;
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wire [31:0] ext_rst_vector_0;
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wire soft_int_0;
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wire timer_int_0;
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wire rst_1 /*verilator public*/;
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wire wb_i_stb_1;
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wire wb_i_cyc_1;
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//wire wb_i_we_1;
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//wire [3:0] wb_i_sel_1;
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wire [31:2] wb_i_adr_1;
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//wire [31:0] wb_i_datw_1;
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wire wb_i_ack_1;
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wire [31:0] wb_i_datr_1;
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wire wb_d_stb_1;
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wire wb_d_cyc_1;
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wire wb_d_we_1;
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wire [3:0] wb_d_sel_1;
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wire [31:2] wb_d_adr_1;
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wire [31:0] wb_d_datw_1;
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wire wb_d_ack_1;
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wire [31:0] wb_d_datr_1;
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wire ext_int_1;
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wire ext_int_s_1;
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wire [31:0] ext_rst_vector_1;
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wire soft_int_1;
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wire timer_int_1;
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wire rst_2 /*verilator public*/;
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wire wb_i_stb_2;
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wire wb_i_cyc_2;
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//wire wb_i_we_2;
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//wire [3:0] wb_i_sel_2;
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wire [31:2] wb_i_adr_2;
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//wire [31:0] wb_i_datw_2;
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wire wb_i_ack_2;
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wire [31:0] wb_i_datr_2;
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wire wb_d_stb_2;
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wire wb_d_cyc_2;
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wire wb_d_we_2;
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wire [3:0] wb_d_sel_2;
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wire [31:2] wb_d_adr_2;
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wire [31:0] wb_d_datw_2;
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wire wb_d_ack_2;
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wire [31:0] wb_d_datr_2;
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wire ext_int_2;
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wire ext_int_s_2;
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wire [31:0] ext_rst_vector_2;
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wire soft_int_2;
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wire timer_int_2;
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wire rst_3 /*verilator public*/;
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wire wb_i_stb_3;
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wire wb_i_cyc_3;
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//wire wb_i_we_3;
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//wire [3:0] wb_i_sel_3;
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wire [31:2] wb_i_adr_3;
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//wire [31:0] wb_i_datw_3;
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wire wb_i_ack_3;
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wire [31:0] wb_i_datr_3;
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wire wb_d_stb_3;
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wire wb_d_cyc_3;
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wire wb_d_we_3;
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wire [3:0] wb_d_sel_3;
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wire [31:2] wb_d_adr_3;
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wire [31:0] wb_d_datw_3;
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wire wb_d_ack_3;
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wire [31:0] wb_d_datr_3;
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wire ext_int_3;
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wire ext_int_s_3;
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wire [31:0] ext_rst_vector_3;
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wire soft_int_3;
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wire timer_int_3;
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// core in/out viewed by core
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assign c0_out = {wb_i_stb_0, wb_i_cyc_0, 1'b0 , 4'b0, {wb_i_adr_0, 2'b0}, 32'b0, 1'b0, 32'b0, 24'b0,
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wb_d_stb_0, wb_d_cyc_0, wb_d_we_0, wb_d_sel_0, {wb_d_adr_0, 2'b0}, wb_d_datw_0, 1'b0, 32'b0, 24'b0,
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ext_int_0, ext_int_s_0, ext_rst_vector_0, soft_int_0, timer_int_0, 92'b0};
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assign {wb_i_ack_0, wb_i_datr_0} = c0_in[`WB2_I_WB_IN_START:`WB2_I_WB_IN_START-32];
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assign {wb_d_ack_0, wb_d_datr_0} = c0_in[`WB2_D_WB_IN_START:`WB2_D_WB_IN_START-32];
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assign c1_out = {wb_i_stb_1, wb_i_cyc_1, 1'b0 , 4'b0, {wb_i_adr_1, 2'b0}, 32'b0, 1'b0, 32'b0, 24'b0,
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wb_d_stb_1, wb_d_cyc_1, wb_d_we_1, wb_d_sel_1, {wb_d_adr_1, 2'b0}, wb_d_datw_1, 1'b0, 32'b0, 24'b0,
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ext_int_1, ext_int_s_1, ext_rst_vector_1, soft_int_1, timer_int_1, 92'b0};
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assign {wb_i_ack_1, wb_i_datr_1} = c1_in[`WB2_I_WB_IN_START:`WB2_I_WB_IN_START-32];
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assign {wb_d_ack_1, wb_d_datr_1} = c1_in[`WB2_D_WB_IN_START:`WB2_D_WB_IN_START-32];
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assign c2_out = {wb_i_stb_2, wb_i_cyc_2, 1'b0 , 4'b0, {wb_i_adr_2, 2'b0}, 32'b0, 1'b0, 32'b0, 24'b0,
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wb_d_stb_2, wb_d_cyc_2, wb_d_we_2, wb_d_sel_2, {wb_d_adr_2, 2'b0}, wb_d_datw_2, 1'b0, 32'b0, 24'b0,
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ext_int_2, ext_int_s_2, ext_rst_vector_2, soft_int_2, timer_int_2, 92'b0};
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assign {wb_i_ack_2, wb_i_datr_2} = c2_in[`WB2_I_WB_IN_START:`WB2_I_WB_IN_START-32];
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assign {wb_d_ack_2, wb_d_datr_2} = c2_in[`WB2_D_WB_IN_START:`WB2_D_WB_IN_START-32];
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assign c3_out = {wb_i_stb_3, wb_i_cyc_3, 1'b0 , 4'b0, {wb_i_adr_3, 2'b0}, 32'b0, 1'b0, 32'b0, 24'b0,
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wb_d_stb_3, wb_d_cyc_3, wb_d_we_3, wb_d_sel_3, {wb_d_adr_3, 2'b0}, wb_d_datw_3, 1'b0, 32'b0, 24'b0,
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ext_int_3, ext_int_s_3, ext_rst_vector_3, soft_int_3, timer_int_3, 92'b0};
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assign {wb_i_ack_3, wb_i_datr_3} = c3_in[`WB2_I_WB_IN_START:`WB2_I_WB_IN_START-32];
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assign {wb_d_ack_3, wb_d_datr_3} = c3_in[`WB2_D_WB_IN_START:`WB2_D_WB_IN_START-32];
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// bus in/out viewed by bridge
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assign {wb_i_stb, wb_i_cyc} = wb_out[`BUS_WB2_I_OUT_START:`BUS_WB2_I_OUT_START-1];
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assign wb_i_adr = wb_out[`BUS_WB2_I_OUT_START-7:`BUS_WB2_I_OUT_START-38];
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assign {wb_d_stb, wb_d_cyc, wb_d_we, wb_d_sel} = wb_out[`BUS_WB2_D_OUT_START:`BUS_WB2_D_OUT_START-6];
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assign wb_d_adr = wb_out[`BUS_WB2_D_OUT_START-7:`BUS_WB2_D_OUT_START-38];
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assign wb_d_datw = wb_out[`BUS_WB2_D_OUT_START-39:`BUS_WB2_D_OUT_START-70];
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assign wb_in = {wb_i_ack, wb_i_datr, 31'b0, wb_d_ack, wb_d_datr, 31'b0};
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// may want to control resets with config, etc.
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//assign rst_0 = rst;
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//assign rst_1 = rst;
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//assign rst_2 = rst;
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//assign rst_3 = rst;
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A2WB #(
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.CORE_TYPES(CORE_TYPES),
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.BUS_TYPE(BUS_TYPE)
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) bridge (
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.clk(clk),
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.rst(rst),
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.cores_in({c0_out, c1_out, c2_out, c3_out}),
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.cores_out({c0_in, c1_in, c2_in, c3_in}),
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.bus_in(wb_in),
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.bus_out(wb_out)
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);
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A2P_4K1W c0 (
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.clk(clk),
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.reset(rst_0),
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.iBusWB_STB(wb_i_stb_0),
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.iBusWB_CYC(wb_i_cyc_0),
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.iBusWB_ADR(wb_i_adr_0),
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.iBusWB_WE(),
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.iBusWB_SEL(),
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.iBusWB_DAT_MOSI(),
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.iBusWB_ACK(wb_i_ack_0),
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.iBusWB_DAT_MISO(wb_i_datr_0),
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.iBusWB_ERR(1'd0),
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.iBusWB_BTE(),
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.iBusWB_CTI(),
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.dBusWB_STB(wb_d_stb_0),
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.dBusWB_CYC(wb_d_cyc_0),
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.dBusWB_WE(wb_d_we_0),
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.dBusWB_SEL(wb_d_sel_0),
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.dBusWB_ADR(wb_d_adr_0),
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.dBusWB_DAT_MOSI(wb_d_datw_0),
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.dBusWB_ACK(wb_d_ack_0),
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.dBusWB_DAT_MISO(wb_d_datr_0),
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.dBusWB_ERR(1'd0),
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.dBusWB_BTE(),
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.dBusWB_CTI(),
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.externalInterrupt(ext_int_0),
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.externalInterruptS(ext_int_s_0),
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.externalResetVector(ext_rst_vector_0),
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.softwareInterrupt(soft_int_0),
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.timerInterrupt(timer_int_0)
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);
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A2P_4K1W c1 (
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.clk(clk),
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.reset(rst_1),
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.iBusWB_STB(wb_i_stb_1),
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.iBusWB_CYC(wb_i_cyc_1),
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.iBusWB_ADR(wb_i_adr_1),
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.iBusWB_WE(),
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.iBusWB_SEL(),
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.iBusWB_DAT_MOSI(),
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.iBusWB_ACK(wb_i_ack_1),
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.iBusWB_DAT_MISO(wb_i_datr_1),
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.iBusWB_ERR(1'd0),
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.iBusWB_BTE(),
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.iBusWB_CTI(),
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.dBusWB_STB(wb_d_stb_1),
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.dBusWB_CYC(wb_d_cyc_1),
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.dBusWB_WE(wb_d_we_1),
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.dBusWB_SEL(wb_d_sel_1),
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.dBusWB_ADR(wb_d_adr_1),
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.dBusWB_DAT_MOSI(wb_d_datw_1),
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.dBusWB_ACK(wb_d_ack_1),
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.dBusWB_DAT_MISO(wb_d_datr_1),
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.dBusWB_ERR(1'd0),
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.dBusWB_BTE(),
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.dBusWB_CTI(),
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.externalInterrupt(ext_int_1),
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.externalInterruptS(ext_int_s_1),
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.externalResetVector(ext_rst_vector_1),
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.softwareInterrupt(soft_int_1),
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.timerInterrupt(timer_int_1)
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);
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A2P_4K1W c2 (
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.clk(clk),
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.reset(rst_2),
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.iBusWB_STB(wb_i_stb_2),
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.iBusWB_CYC(wb_i_cyc_2),
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.iBusWB_ADR(wb_i_adr_2),
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.iBusWB_WE(),
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.iBusWB_SEL(),
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.iBusWB_DAT_MOSI(),
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.iBusWB_ACK(wb_i_ack_2),
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.iBusWB_DAT_MISO(wb_i_datr_2),
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.iBusWB_ERR(1'd0),
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.iBusWB_BTE(),
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.iBusWB_CTI(),
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.dBusWB_STB(wb_d_stb_2),
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.dBusWB_CYC(wb_d_cyc_2),
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.dBusWB_WE(wb_d_we_2),
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.dBusWB_SEL(wb_d_sel_2),
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.dBusWB_ADR(wb_d_adr_2),
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.dBusWB_DAT_MOSI(wb_d_datw_2),
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.dBusWB_ACK(wb_d_ack_2),
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.dBusWB_DAT_MISO(wb_d_datr_2),
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.dBusWB_ERR(1'd0),
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.dBusWB_BTE(),
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.dBusWB_CTI(),
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.externalInterrupt(ext_int_2),
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.externalInterruptS(ext_int_s_2),
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.externalResetVector(ext_rst_vector_2),
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.softwareInterrupt(soft_int_2),
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.timerInterrupt(timer_int_2)
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);
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A2P_4K1W c3 (
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.clk(clk),
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.reset(rst_3),
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.iBusWB_STB(wb_i_stb_3),
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.iBusWB_CYC(wb_i_cyc_3),
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.iBusWB_ADR(wb_i_adr_3),
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.iBusWB_WE(),
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.iBusWB_SEL(),
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.iBusWB_DAT_MOSI(),
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.iBusWB_ACK(wb_i_ack_3),
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.iBusWB_DAT_MISO(wb_i_datr_3),
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.iBusWB_ERR(1'd0),
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.iBusWB_BTE(),
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.iBusWB_CTI(),
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.dBusWB_STB(wb_d_stb_3),
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.dBusWB_CYC(wb_d_cyc_3),
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.dBusWB_WE(wb_d_we_3),
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.dBusWB_SEL(wb_d_sel_3),
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.dBusWB_ADR(wb_d_adr_3),
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.dBusWB_DAT_MOSI(wb_d_datw_3),
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.dBusWB_ACK(wb_d_ack_3),
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.dBusWB_DAT_MISO(wb_d_datr_3),
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.dBusWB_ERR(1'd0),
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.dBusWB_BTE(),
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.dBusWB_CTI(),
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.externalInterrupt(ext_int_3),
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.externalInterruptS(ext_int_s_3),
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.externalResetVector(ext_rst_vector_3),
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.softwareInterrupt(soft_int_3),
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.timerInterrupt(timer_int_3)
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);
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endmodule
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