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34 lines
444 B
Verilog
34 lines
444 B
Verilog
//wtf doesnt do nothin!
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module OSERDESE2 #(
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parameter DATA_RATE_OQ,
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parameter DATA_RATE_TQ,
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parameter DATA_WIDTH,
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parameter SERDES_MODE,
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parameter TRISTATE_WIDTH
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)
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(
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input CLK,
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input CLKDIV,
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input DDLY,
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input RST,
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input D1,
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input D2,
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input D3,
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input D4,
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input D5,
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input D6,
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input D7,
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input D8,
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input OCE,
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input OFB,
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input T1,
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input TCE,
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output OQ,
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output TQ
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);
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endmodule
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