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a2p/rtl/powerp
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wtf 760391234c powerp info 4 years ago
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readme.md powerp info 4 years ago

readme.md

PowerP

  • test environment for ASIC implementation

FPGA Environment

  • Litex SOC, Wishbone bus/peripherals

  • Minimum requirement: low-cost dev board with GTP I/O (6G serial):

    https://github.com/ChinaQMTECH/XC7A100T-200T_Wukong_Board

  • 2+ cores

  • 2 OMI host stacks (Wishbone slaves)

  • 2 OMI memory stacks (partitioned DDR)

  • Wrapback serial connections for single-FPGA testing (2 pairs of OMI links)