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readme.md
PowerP
- test environment for ASIC implementation
FPGA Environment
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Litex SOC, Wishbone bus/peripherals
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Minimum requirement: low-cost dev board with GTP I/O (6G serial):
https://github.com/ChinaQMTECH/XC7A100T-200T_Wukong_Board -
2+ cores
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2 OMI host stacks (Wishbone slaves)
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2 OMI memory stacks (partitioned DDR)
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Wrapback serial connections for single-FPGA testing (2 pairs of OMI links)