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124 lines
3.4 KiB
Python
124 lines
3.4 KiB
Python
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# virtual platform for efabless caravel user area
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# tots general-purpose (no defined i/o for specific site being built)
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from litex.build.generic_platform import *
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'''
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defines.v:`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
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defines.v:`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
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module user_project_wrapper #(
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parameter BITS = 32
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// Analog (direct connection to GPIO pad---use with caution)
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// Note that analog I/O is not available on the 7 lowest-numbered
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// GPIO pads, and so the analog_io indexing is offset from the
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// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
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inout [`MPRJ_IO_PADS-10:0] analog_io,
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// Independent clock (on independent integer divider)
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input user_clock2,
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// User maskable interrupt signals
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output [2:0] user_irq
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);
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'''
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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('wb_clk_i', 0, Pins(1)),
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('user_clock2', 0, Pins(1)),
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("wb_rst_i", 0, Pins(1)),
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# WB Slave
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('wbs_stb_i', 0, Pins(1)),
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('wbs_cyc_i', 0, Pins(1)),
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('wbs_we_i', 0, Pins(1)),
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('wbs_sel_i', 0, Pins(4)),
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('wbs_adr_i', 0, Pins(32)),
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('wbs_dat_i', 0, Pins(32)),
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('wbs_ack_o', 0, Pins(1)),
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('wbs_dat_o', 0, Pins(32)),
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# GPIO
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('in_in', 0, Pins(19)),
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('in_out', 0, Pins(19)),
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('in_oeb', 0, Pins(1)),
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('analog_in', 0, Pins(1)),
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# Misc
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('user_irq', 0, Pins(3)),
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# LA
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('la_data_in', 0, Pins(128)),
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('la_data_out', 0, Pins(128)),
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('la_oenb', 0, Pins(128))
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]
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# Platform -----------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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# this somehow appears to work
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from platforms.virtual import VirtualPlatform
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class Platform(VirtualPlatform):
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default_clk_name = 'wb_clk_i'
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default_clk_period = 1e9/50e6
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def __init__(self):
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VirtualPlatform.__init__(self, 'caravel_user', _io)
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def do_finalize(self, fragment):
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VirtualPlatform.do_finalize(self, fragment)
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'''
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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class Platform(XilinxPlatform):
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default_clk_name = 'wb_clk_i'
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default_clk_period = 1e9/50e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, toolchain="vivado")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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''' |