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a2p/build/openroad/logs/clk_100_allrams/2_1_floorplan.log

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[WTF] clk_period=10.0
number instances in verilog is 419899
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 33874 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um
==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 v _334882_/B (sky130_fd_sc_hd__nand2_1)
0.05 0.05 0.05 ^ _334882_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.05 0.01 0.06 ^ _392865_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.06 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.11 0.11 library removal time
0.11 data required time
-----------------------------------------------------------------------------
0.11 data required time
-0.06 data arrival time
-----------------------------------------------------------------------------
-0.05 slack (VIOLATED)
Startpoint: iBusWB_DAT_MISO[0] (input port clocked by clk)
Endpoint: _336820_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[0] (in)
1 0.00 iBusWB_DAT_MISO[0] (net)
0.00 0.00 0.00 ^ _336820_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _336820_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)
==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _334847_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _334847_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _392865_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
9.85 slack (MET)
Startpoint: _347929_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _347929_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.60 1.38 1.38 ^ _347929_/Q (sky130_fd_sc_hd__dfxtp_1)
43 0.17 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.60 0.00 1.38 ^ _170832_/A (sky130_fd_sc_hd__nor2b_1)
0.29 0.25 1.64 v _170832_/Y (sky130_fd_sc_hd__nor2b_1)
5 0.01 _057084_ (net)
0.29 0.00 1.64 v _170981_/B1 (sky130_fd_sc_hd__a21oi_1)
0.17 0.21 1.85 ^ _170981_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _057164_ (net)
0.17 0.00 1.85 ^ _170982_/B (sky130_fd_sc_hd__nor2_1)
0.05 0.07 1.92 v _170982_/Y (sky130_fd_sc_hd__nor2_1)
2 0.00 _057165_ (net)
0.05 0.00 1.92 v _170984_/A3 (sky130_fd_sc_hd__o31a_1)
3.37 2.89 4.81 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 0.84 _057167_ (net)
3.37 0.00 4.82 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
1.55 2.46 7.27 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.08 _057195_ (net)
1.55 0.00 7.28 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.39 0.39 7.67 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.02 _059918_ (net)
0.39 0.00 7.67 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
894.69 658.29 665.96 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 47.78 _060082_ (net)
894.69 0.00 665.96 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
21.06 5385.83 6051.78 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.06 0.00 6051.79 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6060.04 data arrival time
0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 4.81 library setup time
4.81 data required time
-----------------------------------------------------------------------------
4.81 data required time
-6060.04 data arrival time
-----------------------------------------------------------------------------
-6055.23 slack (VIOLATED)
==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _334847_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _334847_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _392865_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
9.85 slack (MET)
Startpoint: _347929_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _347929_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.60 1.38 1.38 ^ _347929_/Q (sky130_fd_sc_hd__dfxtp_1)
43 0.17 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.60 0.00 1.38 ^ _170832_/A (sky130_fd_sc_hd__nor2b_1)
0.29 0.25 1.64 v _170832_/Y (sky130_fd_sc_hd__nor2b_1)
5 0.01 _057084_ (net)
0.29 0.00 1.64 v _170981_/B1 (sky130_fd_sc_hd__a21oi_1)
0.17 0.21 1.85 ^ _170981_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _057164_ (net)
0.17 0.00 1.85 ^ _170982_/B (sky130_fd_sc_hd__nor2_1)
0.05 0.07 1.92 v _170982_/Y (sky130_fd_sc_hd__nor2_1)
2 0.00 _057165_ (net)
0.05 0.00 1.92 v _170984_/A3 (sky130_fd_sc_hd__o31a_1)
3.37 2.89 4.81 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 0.84 _057167_ (net)
3.37 0.00 4.82 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
1.55 2.46 7.27 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.08 _057195_ (net)
1.55 0.00 7.28 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.39 0.39 7.67 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.02 _059918_ (net)
0.39 0.00 7.67 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
894.69 658.29 665.96 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 47.78 _060082_ (net)
894.69 0.00 665.96 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
21.06 5385.83 6051.78 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.06 0.00 6051.79 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6060.04 data arrival time
0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 4.81 library setup time
4.81 data required time
-----------------------------------------------------------------------------
4.81 data required time
-6060.04 data arrival time
-----------------------------------------------------------------------------
-6055.23 slack (VIOLATED)
==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -14775986.00
==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -6055.23
==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -6055.23
==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[0]/CLK ^
0.00 0.00 0.26
==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.98e-01 1.16e-02 9.12e-07 4.09e-01 18.1%
Combinational 1.75e+00 9.21e-02 8.63e-07 1.84e+00 81.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.15e+00 1.04e-01 1.77e-06 2.26e+00 100.0%
95.4% 4.6% 0.0%
==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 4541698 u^2 23% utilization.
Elapsed time: 2:35.18[h:]min:sec. CPU time: user 154.64 sys 0.51 (99%). Peak memory: 1373324KB.
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