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63baf02c66 | 3 years ago | |
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readme.md | 3 years ago |
readme.md
L2 Multicore
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Multicore bridge to WB
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generate 1-4 core interfaces (possibly mixed)
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slave WB-I, slave WB-D, OPMC extension (opcode/WIMG/...)
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a2i/a2o out-of-order/credits/... style
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configurable load and store queues per interface (if pipelined/credited interfaces)
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point-of-coherency/snoop/sync/... logic
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configurable-size shared L2 (extra tags for pinning, etc.?)
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WB-I, WB-D master
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