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54 lines
1.5 KiB
Makefile
54 lines
1.5 KiB
Makefile
# design and tech
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export DESIGN_NICKNAME = a2p
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export DESIGN_NAME = A2P_WB
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export PLATFORM = sky130hd
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export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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$(info Source files:)
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$(info $(VERILOG_FILES))
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$(info ..................................................)
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# design and tech
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unit = a2p
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# 5% utilization
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#[INFO PDN-0013] Inserting stdcell grid - grid
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#Command terminated by signal 9
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#export DIE_AREA = 0 0 10000 10000
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#export CORE_AREA = 100 100 10000 10000
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# 21% utilization
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#Error: resize.tcl, 88 invalid command name "sta::max_slew_violation_count"
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export DIE_AREA = 0 0 5000 5000
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export CORE_AREA = 100 100 5000 5000
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#export CORE_UTILIZATION = 100
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#export CORE_ASPECT_RATIO = 1
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#export CORE_MARGIN = 2
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# a2o fu stuff
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# keeps hierarchy of some cells even if flattening
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#export PRESERVE_CELLS ?= tri_144x78_2r4w
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# no flatten
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#export SYNTH_NO_FLAT ?= 1
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# don't optimize tri_144x78_2r4w
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#export SYNTH_OPT_SELECTION ?= fu
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#export PLACE_DENSITY ?= 0.80
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# also set cycle time in constraint.sdc! derive it there from this?
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#export ABC_CLOCK_PERIOD_IN_PS ?= 10000
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#export ABC_DEFAULT_SCRIPT ?= 1
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# fanout doesn't get adjusted to fix paths? or resizer not working
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export SYNTH_MAX_FANOUT ?= 32
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export SYNTH_MAX_TRAN ?= 100
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#wtf can't specify in resizer anymore?
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#export RS_BUF_CELL ?= BUF_X4
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#export RS_MAX_FO ?= 20
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export REPORT_SLACK_MAX_PATHS ?= 100
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