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<img align="right" src="doc/img/bob_64x64.jpg">
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# ToySRAM
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## A test site for a high-specific-bandwidth memory design
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* We make high-specific-bandwidth multiport memories child’s play
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* We make 10T SRAM a first-class citizen, and use pumping and replication for high frequency and additional ports
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## Description
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The goal is to demonstrate specific bandwidth results from 90nm to 2nm, and use
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the basic design to grow as many ports as necessary through replication, to
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produce more efficient processors and accelerators with *less circuit-design effort*.
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What is specific bandwidth?
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* It measures the read and write bandwidth per unit area
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* Bandwidth per unit area is an analog to specific gravity, which is mass per unit volume
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* It's more encompassing than bit density, which drives complexity to improve bandwidth
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Why does Toy-SRAM do so well?
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* It's enhanced by having a 10T SRAM/2 read ports/1 write port
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* It supports low-cost super-pipelining (2x+ the system frequency, without latch overhead)
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* It enables energy-efficient ultralow-voltage operation by avoiding read disturb
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Specific bandwidth can be expressed with two metrics:
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* Technology dependent “X TB/(sec * mm 2 )”
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* Technology independent “Y 1/(FO4 delay * PC PITCH * min horizontal metal pitch)”
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<img align="left" width="40%" src="/custom/layout/sram_sp.png">
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<img align="right" width="40%" src="/custom/layout/sram_dp.png">
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<br clear="all" />
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## Links
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* skywater-pdk.slack.com#toysram
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