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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Logical wrapper for 64x72 array (SDR)
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// Configurable for read latching
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`timescale 1 ns / 1 ns
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module ra_64x72_2r1w #(
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parameter GENMODE, // 0=NoDelay, 1=Delay
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parameter LATCHRD = 1 // 1=latch read data, 0=unlatched
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) (
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input clk,
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input reset,
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input strobe,
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input rd_enb_0,
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input [0:5] rd_adr_0,
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output [0:71] rd_dat_0,
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input rd_enb_1,
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input [0:5] rd_adr_1,
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output [0:71] rd_dat_1,
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input wr_enb_0,
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input [0:5] wr_adr_0,
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input [0:71] wr_dat_0
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);
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reg rd_enb_0_q;
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reg [0:5] rd_adr_0_q;
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reg [0:71] rd_dat_0_q;
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reg rd_enb_1_q;
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reg [0:5] rd_adr_1_q;
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reg [0:71] rd_dat_1_q;
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reg wr_enb_0_q;
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reg [0:5] wr_adr_0_q;
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reg [0:71] wr_dat_0_q;
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wire rd0_c_na0;
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wire rd0_c_a0;
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wire rd0_na1_na2;
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wire rd0_na1_a2;
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wire rd0_a1_na2;
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wire rd0_a1_a2;
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wire rd0_na3;
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wire rd0_a3;
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wire rd0_na4_na5;
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wire rd0_na4_a5;
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wire rd0_a4_na5;
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wire rd0_a4_a5;
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wire [0:71] ra_rd_dat_0;
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wire rd1_c_na0;
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wire rd1_c_a0;
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wire rd1_na1_na2;
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wire rd1_na1_a2;
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wire rd1_a1_na2;
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wire rd1_a1_a2;
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wire rd1_na3;
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wire rd1_a3;
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wire rd1_na4_na5;
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wire rd1_na4_a5;
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wire rd1_a4_na5;
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wire rd1_a4_a5;
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wire [0:71] ra_rd_dat_1;
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wire wr0_c_na0;
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wire wr0_c_a0;
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wire wr0_na1_na2;
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wire wr0_na1_a2;
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wire wr0_a1_na2;
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wire wr0_a1_a2;
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wire wr0_na3;
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wire wr0_a3;
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wire wr0_na4_na5;
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wire wr0_na4_a5;
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wire wr0_a4_na5;
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wire wr0_a4_a5;
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wire ra_wr_enb_0;
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wire [0:5] ra_wr_adr_0;
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wire [0:71] ra_wr_dat_0;
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wire strobe_int;
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// latch inputs
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// reset all; only enb required
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always @ (posedge clk) begin
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if (reset == 1'b1) begin
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rd_enb_0_q <= 0;
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rd_adr_0_q <= 0;
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rd_enb_1_q <= 0;
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rd_adr_1_q <= 0;
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wr_enb_0_q <= 0;
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wr_adr_0_q <= 0;
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wr_dat_0_q <= 0;
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end else begin
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rd_enb_0_q <= rd_enb_0;
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rd_adr_0_q <= rd_adr_0;
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rd_enb_1_q <= rd_enb_1;
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rd_adr_1_q <= rd_adr_1;
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wr_enb_0_q <= wr_enb_0;
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wr_adr_0_q <= wr_adr_0;
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wr_dat_0_q <= wr_dat_0;
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end
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end
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// latch read data conditionally
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generate
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if (LATCHRD) begin
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always @ (posedge clk) begin
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rd_dat_0_q <= ra_rd_dat_0;
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rd_dat_1_q <= ra_rd_dat_1;
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end
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assign rd_dat_0 = rd_dat_0_q;
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assign rd_dat_1 = rd_dat_1_q;
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end else begin
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assign rd_dat_0 = ra_rd_dat_0;
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assign rd_dat_1 = ra_rd_dat_1;
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end
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endgenerate
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assign strobe_int = strobe;
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address_clock #(
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.GENMODE(GENMODE)
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) add_clk (
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.strobe (strobe_int),
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.rd_enb_0 (rd_enb_0_q),
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.rd_adr_0 (rd_adr_0_q),
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.rd_enb_1 (rd_enb_1_q),
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.rd_adr_1 (rd_adr_1_q),
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.wr_enb_0 (wr_enb_0_q),
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.wr_adr_0 (wr_adr_0_q),
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.rd0_c_na0 (rd0_c_na0),
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.rd0_c_a0 (rd0_c_a0),
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.rd0_na1_na2 (rd0_na1_na2),
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.rd0_na1_a2 (rd0_na1_a2),
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.rd0_a1_na2 (rd0_a1_na2),
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.rd0_a1_a2 (rd0_a1_a2),
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.rd0_na3 (rd0_na3),
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.rd0_a3 (rd0_a3),
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.rd0_na4_na5 (rd0_na4_na5),
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.rd0_na4_a5 (rd0_na4_a5),
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.rd0_a4_na5 (rd0_a4_na5),
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.rd0_a4_a5 (rd0_a4_a5),
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.rd1_c_na0 (rd1_c_na0),
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.rd1_c_a0 (rd1_c_a0),
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.rd1_na1_na2 (rd1_na1_na2),
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.rd1_na1_a2 (rd1_na1_a2),
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.rd1_a1_na2 (rd1_a1_na2),
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.rd1_a1_a2 (rd1_a1_a2),
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.rd1_na3 (rd1_na3),
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.rd1_a3 (rd1_a3),
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.rd1_na4_na5 (rd1_na4_na5),
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.rd1_na4_a5 (rd1_na4_a5),
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.rd1_a4_na5 (rd1_a4_na5),
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.rd1_a4_a5 (rd1_a4_a5),
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.wr0_c_na0 (wr0_c_na0),
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.wr0_c_a0 (wr0_c_a0),
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.wr0_na1_na2 (wr0_na1_na2),
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.wr0_na1_a2 (wr0_na1_a2),
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.wr0_a1_na2 (wr0_a1_na2),
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.wr0_a1_a2 (wr0_a1_a2),
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.wr0_na3 (wr0_na3),
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.wr0_a3 (wr0_a3),
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.wr0_na4_na5 (wr0_na4_na5),
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.wr0_na4_a5 (wr0_na4_a5),
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.wr0_a4_na5 (wr0_a4_na5),
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.wr0_a4_a5 (wr0_a4_a5)
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);
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regfile_shard_64x24_2r1w_comp ra0(
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.rd0_c_na0 (rd0_c_na0),
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.rd0_c_a0 (rd0_c_a0),
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.rd0_na1_na2 (rd0_na1_na2),
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.rd0_na1_a2 (rd0_na1_a2),
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.rd0_a1_na2 (rd0_a1_na2),
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.rd0_a1_a2 (rd0_a1_a2),
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.rd0_na3 (rd0_na3),
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.rd0_a3 (rd0_a3),
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.rd0_na4_na5 (rd0_na4_na5),
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.rd0_na4_a5 (rd0_na4_a5),
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.rd0_a4_na5 (rd0_a4_na5),
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.rd0_a4_a5 (rd0_a4_a5),
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.rd0_dat (ra_rd_dat_0[0:23]),
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.rd1_c_na0 (rd1_c_na0),
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.rd1_c_a0 (rd1_c_a0),
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.rd1_na1_na2 (rd1_na1_na2),
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.rd1_na1_a2 (rd1_na1_a2),
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.rd1_a1_na2 (rd1_a1_na2),
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.rd1_a1_a2 (rd1_a1_a2),
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.rd1_na3 (rd1_na3),
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.rd1_a3 (rd1_a3),
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.rd1_na4_na5 (rd1_na4_na5),
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.rd1_na4_a5 (rd1_na4_a5),
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.rd1_a4_na5 (rd1_a4_na5),
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.rd1_a4_a5 (rd1_a4_a5),
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.rd1_dat (ra_rd_dat_1[0:23]),
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.wr0_c_na0 (wr0_c_na0),
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.wr0_c_a0 (wr0_c_a0),
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.wr0_na1_na2 (wr0_na1_na2),
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.wr0_na1_a2 (wr0_na1_a2),
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.wr0_a1_na2 (wr0_a1_na2),
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.wr0_a1_a2 (wr0_a1_a2),
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.wr0_na3 (wr0_na3),
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.wr0_a3 (wr0_a3),
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.wr0_na4_na5 (wr0_na4_na5),
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.wr0_na4_a5 (wr0_na4_a5),
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.wr0_a4_na5 (wr0_a4_na5),
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.wr0_a4_a5 (wr0_a4_a5),
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.wr0_dat (wr_dat_0_q[0:23])
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);
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regfile_shard_64x24_2r1w_comp ra1(
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.rd0_c_na0 (rd0_c_na0),
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.rd0_c_a0 (rd0_c_a0),
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.rd0_na1_na2 (rd0_na1_na2),
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.rd0_na1_a2 (rd0_na1_a2),
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.rd0_a1_na2 (rd0_a1_na2),
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.rd0_a1_a2 (rd0_a1_a2),
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.rd0_na3 (rd0_na3),
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.rd0_a3 (rd0_a3),
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.rd0_na4_na5 (rd0_na4_na5),
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.rd0_na4_a5 (rd0_na4_a5),
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.rd0_a4_na5 (rd0_a4_na5),
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.rd0_a4_a5 (rd0_a4_a5),
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.rd0_dat (ra_rd_dat_0[24:47]),
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.rd1_c_na0 (rd1_c_na0),
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.rd1_c_a0 (rd1_c_a0),
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|
.rd1_na1_na2 (rd1_na1_na2),
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|
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|
.rd1_na1_a2 (rd1_na1_a2),
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|
|
|
|
.rd1_a1_na2 (rd1_a1_na2),
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|
|
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|
.rd1_a1_a2 (rd1_a1_a2),
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|
|
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|
.rd1_na3 (rd1_na3),
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|
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|
.rd1_a3 (rd1_a3),
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|
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|
.rd1_na4_na5 (rd1_na4_na5),
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|
.rd1_na4_a5 (rd1_na4_a5),
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|
|
|
|
|
.rd1_a4_na5 (rd1_a4_na5),
|
|
|
|
|
|
.rd1_a4_a5 (rd1_a4_a5),
|
|
|
|
|
|
.rd1_dat (ra_rd_dat_1[24:47]),
|
|
|
|
|
|
|
|
|
|
|
|
.wr0_c_na0 (wr0_c_na0),
|
|
|
|
|
|
.wr0_c_a0 (wr0_c_a0),
|
|
|
|
|
|
.wr0_na1_na2 (wr0_na1_na2),
|
|
|
|
|
|
.wr0_na1_a2 (wr0_na1_a2),
|
|
|
|
|
|
.wr0_a1_na2 (wr0_a1_na2),
|
|
|
|
|
|
.wr0_a1_a2 (wr0_a1_a2),
|
|
|
|
|
|
.wr0_na3 (wr0_na3),
|
|
|
|
|
|
.wr0_a3 (wr0_a3),
|
|
|
|
|
|
.wr0_na4_na5 (wr0_na4_na5),
|
|
|
|
|
|
.wr0_na4_a5 (wr0_na4_a5),
|
|
|
|
|
|
.wr0_a4_na5 (wr0_a4_na5),
|
|
|
|
|
|
.wr0_a4_a5 (wr0_a4_a5),
|
|
|
|
|
|
.wr0_dat (wr_dat_0_q[24:47])
|
|
|
|
|
|
|
|
|
|
|
|
);
|
|
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|
|
|
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|
|
|
regfile_shard_64x24_2r1w_comp ra2 (
|
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|
|
|
|
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|
|
|
|
.rd0_c_na0 (rd0_c_na0),
|
|
|
|
|
|
.rd0_c_a0 (rd0_c_a0),
|
|
|
|
|
|
.rd0_na1_na2 (rd0_na1_na2),
|
|
|
|
|
|
.rd0_na1_a2 (rd0_na1_a2),
|
|
|
|
|
|
.rd0_a1_na2 (rd0_a1_na2),
|
|
|
|
|
|
.rd0_a1_a2 (rd0_a1_a2),
|
|
|
|
|
|
.rd0_na3 (rd0_na3),
|
|
|
|
|
|
.rd0_a3 (rd0_a3),
|
|
|
|
|
|
.rd0_na4_na5 (rd0_na4_na5),
|
|
|
|
|
|
.rd0_na4_a5 (rd0_na4_a5),
|
|
|
|
|
|
.rd0_a4_na5 (rd0_a4_na5),
|
|
|
|
|
|
.rd0_a4_a5 (rd0_a4_a5),
|
|
|
|
|
|
.rd0_dat (ra_rd_dat_0[48:71]),
|
|
|
|
|
|
|
|
|
|
|
|
.rd1_c_na0 (rd1_c_na0),
|
|
|
|
|
|
.rd1_c_a0 (rd1_c_a0),
|
|
|
|
|
|
.rd1_na1_na2 (rd1_na1_na2),
|
|
|
|
|
|
.rd1_na1_a2 (rd1_na1_a2),
|
|
|
|
|
|
.rd1_a1_na2 (rd1_a1_na2),
|
|
|
|
|
|
.rd1_a1_a2 (rd1_a1_a2),
|
|
|
|
|
|
.rd1_na3 (rd1_na3),
|
|
|
|
|
|
.rd1_a3 (rd1_a3),
|
|
|
|
|
|
.rd1_na4_na5 (rd1_na4_na5),
|
|
|
|
|
|
.rd1_na4_a5 (rd1_na4_a5),
|
|
|
|
|
|
.rd1_a4_na5 (rd1_a4_na5),
|
|
|
|
|
|
.rd1_a4_a5 (rd1_a4_a5),
|
|
|
|
|
|
.rd1_dat (ra_rd_dat_1[48:71]),
|
|
|
|
|
|
|
|
|
|
|
|
.wr0_c_na0 (wr0_c_na0),
|
|
|
|
|
|
.wr0_c_a0 (wr0_c_a0),
|
|
|
|
|
|
.wr0_na1_na2 (wr0_na1_na2),
|
|
|
|
|
|
.wr0_na1_a2 (wr0_na1_a2),
|
|
|
|
|
|
.wr0_a1_na2 (wr0_a1_na2),
|
|
|
|
|
|
.wr0_a1_a2 (wr0_a1_a2),
|
|
|
|
|
|
.wr0_na3 (wr0_na3),
|
|
|
|
|
|
.wr0_a3 (wr0_a3),
|
|
|
|
|
|
.wr0_na4_na5 (wr0_na4_na5),
|
|
|
|
|
|
.wr0_na4_a5 (wr0_na4_a5),
|
|
|
|
|
|
.wr0_a4_na5 (wr0_a4_na5),
|
|
|
|
|
|
.wr0_a4_a5 (wr0_a4_a5),
|
|
|
|
|
|
.wr0_dat (wr_dat_0_q[48:71])
|
|
|
|
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
