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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Behavioral for 64x24 toysram (sdr or ddr)
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`timescale 1 ps / 1 ps
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module regfile_64x24_2r1w_behav (
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rd0_c_na0,
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rd0_c_a0,
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rd0_na1_na2,
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rd0_na1_a2,
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rd0_a1_na2,
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rd0_a1_a2,
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rd0_na3,
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rd0_a3,
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rd0_na4_na5,
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rd0_na4_a5,
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rd0_a4_na5,
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rd0_a4_a5,
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rd0_dat,
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rd1_c_na0,
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rd1_c_a0,
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rd1_na1_na2,
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rd1_na1_a2,
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rd1_a1_na2,
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rd1_a1_a2,
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rd1_na3,
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rd1_a3,
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rd1_na4_na5,
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rd1_na4_a5,
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rd1_a4_na5,
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rd1_a4_a5,
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rd1_dat,
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wr0_c_na0,
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wr0_c_a0,
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wr0_na1_na2,
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wr0_na1_a2,
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wr0_a1_na2,
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wr0_a1_a2,
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wr0_na3,
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wr0_a3,
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wr0_na4_na5,
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wr0_na4_a5,
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wr0_a4_na5,
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wr0_a4_a5,
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wr0_dat
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);
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input rd0_c_na0;
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input rd0_c_a0;
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input rd0_na1_na2;
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input rd0_na1_a2;
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input rd0_a1_na2;
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input rd0_a1_a2;
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input rd0_na3;
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input rd0_a3;
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input rd0_na4_na5;
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input rd0_na4_a5;
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input rd0_a4_na5;
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input rd0_a4_a5;
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input rd1_c_na0;
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input rd1_c_a0;
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input rd1_na1_na2;
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input rd1_na1_a2;
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input rd1_a1_na2;
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input rd1_a1_a2;
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input rd1_na3;
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input rd1_a3;
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input rd1_na4_na5;
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input rd1_na4_a5;
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input rd1_a4_na5;
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input rd1_a4_a5;
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input wr0_c_na0;
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input wr0_c_a0;
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input wr0_na1_na2;
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input wr0_na1_a2;
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input wr0_a1_na2;
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input wr0_a1_a2;
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input wr0_na3;
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input wr0_a3;
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input wr0_na4_na5;
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input wr0_na4_a5;
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input wr0_a4_na5;
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input wr0_a4_a5;
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output [0:23] rd0_dat;
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output [0:23] rd1_dat;
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input [0:23] wr0_dat;
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wire rd0_enable;
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wire rd1_enable;
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wire wr0_enable;
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wire rd0_a0;
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wire rd0_a1;
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wire rd0_a2;
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wire rd0_a4;
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wire rd0_a5;
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wire rd1_a0;
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wire rd1_a1;
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wire rd1_a2;
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wire rd1_a4;
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wire rd1_a5;
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wire wr0_a0;
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wire wr0_a1;
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wire wr0_a2;
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wire wr0_a4;
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wire wr0_a5;
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// array cells
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reg[0:23] mem[0:63];
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// decode inputs, rd0
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assign rd0_enable = rd0_c_a0 | rd0_c_na0;
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assign rd0_a0 = rd0_c_a0;
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assign rd0_a1 = rd0_a1_a2 | rd0_a1_na2;
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assign rd0_a2 = rd0_a1_a2 | rd0_na1_a2;
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assign rd0_a4 = rd0_a4_a5 | rd0_a4_na5;
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assign rd0_a5 = rd0_a4_a5 | rd0_na4_a5;
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// deocde inputs, rd1
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assign rd1_enable = rd1_c_a0 | rd1_c_na0;
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assign rd1_a0 = rd1_c_a0;
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assign rd1_a1 = rd1_a1_a2 | rd1_a1_na2;
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assign rd1_a2 = rd1_a1_a2 | rd1_na1_a2;
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assign rd1_a4 = rd1_a4_a5 | rd1_a4_na5;
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assign rd1_a5 = rd1_a4_a5 | rd1_na4_a5;
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// decode inputs, wr0
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assign wr0_enable = wr0_c_a0 | wr0_c_na0;
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assign wr0_a0 = wr0_c_a0;
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assign wr0_a1 = wr0_a1_a2 | wr0_a1_na2;
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assign wr0_a2 = wr0_a1_a2 | wr0_na1_a2;
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assign wr0_a4 = wr0_a4_a5 | wr0_a4_na5;
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assign wr0_a5 = wr0_a4_a5 | wr0_na4_a5;
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// read ports
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assign rd0_dat = (rd0_enable) ? mem[{rd0_a0, rd0_a1, rd0_a2, rd0_a3, rd0_a4, rd0_a5}] : 24'bX;
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assign rd1_dat = (rd1_enable) ? mem[{rd1_a0, rd1_a1, rd1_a2, rd1_a3, rd1_a4, rd1_a5}] : 24'bX;
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// write port
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always_latch @* begin
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if (wr0_enable) begin
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#10; // make sure addr settles
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if (wr0_enable) begin
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mem[{wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4, wr0_a5}] = wr0_dat;
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//$display("%0d wr0_en=%h @%0h=%0h", $time, wr0_enable, {wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4, wr0_a5}, mem[{wr0_a0, wr0_a1, wr0_a2, wr0_a3, wr0_a4, wr0_a5}]);
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end
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end
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end
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endmodule
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