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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Test array (SDR)
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// 64 word 72 bit array
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// LCB for strobe generation
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// Config, BIST, etc.
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`timescale 1 ns/1 ps
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`include "toysram.vh"
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module test_ra_sdr ();
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logic clk;
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logic reset;
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logic cfg_wr;
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logic [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
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logic [0:31] bist_ctl;
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logic [0:31] bist_status;
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logic rd_enb_0;
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logic [0:5] rd_adr_0;
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logic [0:71] rd_dat_0;
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logic rd_enb_1;
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logic [0:5] rd_adr_1;
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logic [0:71] rd_dat_1;
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logic wr_enb_0;
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logic [0:5] wr_adr_0;
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logic [0:71] wr_dat_0;
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logic strobe;
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logic [0:`LCBSDR_CONFIGWIDTH-1] cfg;
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logic mux_rd0_enb;
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logic [0:5] mux_rd0_adr;
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logic mux_rd1_enb;
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logic [0:5] mux_rd1_adr;
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logic mux_wr0_enb;
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logic [0:5] mux_wr0_adr;
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logic [0:71] mux_wr0_dat;
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initial
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begin
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$dumpfile("test_ra_sdr.vcd");
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$dumpvars (0,test_ra_sdr.lcb);
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$dumpvars (0,test_ra_sdr.cfig);
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$dumpvars (0,test_ra_sdr.bist);
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$dumpvars (0,test_ra_sdr.ra);
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end
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initial
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begin
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clk = 1'b1;
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forever #5 clk = ~clk;
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end
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ra_lcb_sdr lcb (.clk (clk),
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.reset (reset),
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.cfg (cfg),
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.strobe (strobe));
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ra_cfg_sdr #(.INIT(-1)) cfig (.clk (clk),
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.reset (reset),
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.cfg_wr (cfg_wr),
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.cfg_dat (cfg_dat),
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.cfg (cfg));
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ra_bist_sdr bist (.clk (clk),
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.reset (reset),
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.ctl (bist_ctl),
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.status (bist_status),
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.rd0_enb_in (rd_enb_0),
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.rd0_adr_in (rd_adr_0),
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.rd0_dat (rd_dat_0),
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.rd1_enb_in (rd_enb_1),
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.rd1_adr_in (rd_adr_1),
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.rd1_dat (rd_dat_1),
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.wr0_enb_in (wr_enb_0),
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.wr0_adr_in (wr_adr_0),
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.wr0_dat_in (wr_dat_0),
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.rd0_enb_out (mux_rd0_enb),
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.rd0_adr_out (mux_rd0_adr),
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.rd1_enb_out (mux_rd1_enb),
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.rd1_adr_out (mux_rd1_adr),
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.wr0_enb_out (mux_wr0_enb),
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.wr0_adr_out (mux_wr0_adr),
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.wr0_dat_out (mux_wr0_dat));
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ra_2r1w_64x72_sdr ra (.clk (clk),
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.reset (reset),
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.strobe (strobe),
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.rd_enb_0 (mux_rd0_enb),
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.rd_adr_0 (mux_rd0_adr),
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.rd_dat_0 (rd_dat_0),
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.rd_enb_1 (mux_rd1_enb),
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.rd_adr_1 (mux_rd1_adr),
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.rd_dat_1 (rd_dat_1),
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.wr_enb_0 (mux_wr0_enb),
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.wr_adr_0 (mux_wr0_adr),
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.wr_dat_0 (mux_wr0_dat));
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initial
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begin
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#0 reset = 1'b1;
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#0 wr_enb_0 = 1'b0;
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#0 wr_adr_0 = 6'h0;
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#0 rd_adr_0 = 6'h0;
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#0 rd_adr_1 = 6'h0;
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#0 rd_enb_0 = 1'b0;
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#0 rd_enb_1 = 1'b0;
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#0 bist_ctl = 32'h0;
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#0 cfg_wr = 1'b0;
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#0 cfg_dat = 16'h0;
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#15 reset = 1'b0;
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#400 wr_enb_0 = 1'b1;
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#0 wr_adr_0 = 6'h0;
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#0 wr_adr_0 = 6'b00_0000;
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#0 wr_dat_0 = 6'b00_1111;
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#10 wr_adr_0 = 6'b00_0010;
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#0 wr_dat_0 = 6'b00_1001;
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#10 wr_adr_0 = 6'b00_0100;
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#0 wr_dat_0 = 6'b00_1100;
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#10 wr_adr_0 = 6'b00_0110;
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#0 wr_adr_0 = 6'b00_1101;
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#10 wr_adr_0 = 6'b00_1000;
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#0 wr_adr_0 = 6'b00_1000;
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#5 wr_enb_0 = 0;
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#5 rd_enb_0 = 1;
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#0 rd_enb_1 = 1;
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#10 rd_adr_0 = 6'b00_0000;
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#0 rd_adr_1 = 6'b00_0010;
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#10 rd_adr_0 = 6'b00_0100;
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#0 rd_adr_1 = 6'b00_0110;
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#10 rd_adr_0 = 6'b00_1000;
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#5 rd_enb_0 = 0;
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#0 rd_enb_1 = 0;
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end
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endmodule
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