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@ -32,9 +32,44 @@ Specific bandwidth can be expressed with two metrics:
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* Technology dependent “X TB/(sec * mm 2 )”
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* Technology independent “Y 1/(FO4 delay * PC PITCH * min horizontal metal pitch)”
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<img align="left" width="40%" src="/custom/layout/sram_sp.png">
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<img align="right" width="40%" src="/custom/layout/sram_dp.png">
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<br clear="all" />
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## Array Design (64x24_2R1W)
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#### 2R1W memory cell
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* read bitlines are the NFET part of a domino stage
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<image src="./cell.png">
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#### Subarray
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* 16 word x 12 bit array of memory cells
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#### 64x24_2R1W 'hard' array
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* (8) subarrays
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* (12) addr/strobe inputs per port are decoded to 64 word lines and precharge enable
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* subarray bitlines are precharged and combined with neighbor subarray in local eval cell
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* final data outs are selected from half-array local evals
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#### 64x24_2R1W 'logical' array
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* strobe plus 6 address lines predecoded to 12 array input lines per port
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* port latching
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### Other
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#### SDR/DDR
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* double-pumping the strobe allows 4R2W operation
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#### LSDL
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* a custom LSDL cell can be used to latch the outputs in the array
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## Links
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