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2e11a03ffb
|
2 years ago | |
|---|---|---|
| .. | ||
| build | ||
| sim | 2 years ago | |
| src | 2 years ago | |
| readme.md | ||
readme.md
Logical Array Wrapper
- verilog is in rtl/src/array
- parameter determines sim vs tech during rtl compile
Physical Array
- custom cell(s) to be designed
- custom/
Test Site
- verilog is in rtl/src/site
- supporting logic for test and debug through available Caravel connections
Verification
- rtl/sim/coco
Caravel
- to be incorporated into https://github.com/efabless/caravel flow as a user project area