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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Test array (SDR) wrapper for cocotb/icarus
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// 32 word 32 bit array
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// LCB for strobe generation
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// Config, BIST, etc.
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`timescale 1 ns / 1 ns
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`include "defines.v"
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`include "toysram.vh"
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module test_site (
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`ifdef USE_POWER_PINS
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inout vccd1, // User area 1 1.8V supply
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inout vssd1, // User area 1 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// IRQ
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output [2:0] irq
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);
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initial begin
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$dumpfile ("test_site.vcd");
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$dumpvars;
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#1;
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end
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toysram_site site (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.wbs_stb_i(wbs_stb_i),
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.wbs_cyc_i(wbs_cyc_i),
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.wbs_we_i(wbs_we_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_dat_i(wbs_dat_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_ack_o(wbs_ack_o),
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.wbs_dat_o(wbs_dat_o),
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// Logic Analyzer Signals
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.la_data_in(la_data_in),
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.la_data_out(la_data_out),
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.la_oenb(la_oenb),
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// IOs
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.io_in(io_in),
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.io_out(io_out),
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.io_oeb(io_oeb),
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// IRQ
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.irq(irq)
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);
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endmodule
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