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openpowerwtf 3ae2375de3 sim 64x72 2 years ago
..
build init 2 years ago
sim sim 64x72 2 years ago
src sim 64x72 2 years ago
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readme.md

Logical Array Wrapper

  • verilog is in rtl/src/array
  • parameter determines sim vs tech during rtl compile

Physical Array

  • custom cell(s) to be designed
  • custom/

Test Site

  • verilog is in rtl/src/site
  • supporting logic for test and debug through available Caravel connections

Verification

  • rtl/sim/coco

Caravel