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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Address and clocking synthesized logic for SDR 2r1w 64 word array
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// Two modes:
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// 1. nodelay: for sim, FPGA - clk (SDR) or clk2x (DDR) produce strobe
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// 2. delay: for implementation, strobes are configured, and derived from clk
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`timescale 1 ns / 1 ns
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module address_clock (
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strobe,
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// address ports and associated enable signals
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rd_enb_0,
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rd_adr_0,
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rd_enb_1,
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rd_adr_1,
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wr_enb_0,
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wr_adr_0,
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// predecoded address signal
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// four groups of one hot encoded signals
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// read address 0
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rd0_c_na0,
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rd0_c_a0,
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rd0_na1_na2,
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rd0_na1_a2,
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rd0_a1_na2,
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rd0_a1_a2,
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rd0_na3,
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rd0_a3,
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rd0_na4_na5,
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rd0_na4_a5,
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rd0_a4_na5,
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rd0_a4_a5,
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// read address 1
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rd1_c_na0,
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rd1_c_a0,
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rd1_na1_na2,
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rd1_na1_a2,
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rd1_a1_na2,
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rd1_a1_a2,
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rd1_na3,
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rd1_a3,
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rd1_na4_na5,
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rd1_na4_a5,
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rd1_a4_na5,
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rd1_a4_a5,
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// write address 0
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wr0_c_na0,
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wr0_c_a0,
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wr0_na1_na2,
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wr0_na1_a2,
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wr0_a1_na2,
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wr0_a1_a2,
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wr0_na3,
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wr0_a3,
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wr0_na4_na5,
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wr0_na4_a5,
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wr0_a4_na5,
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wr0_a4_a5
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);
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parameter GENMODE = 0; // 0=NoDelay, 1=Delay
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input strobe;
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// address ports and associated enable signals
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input rd_enb_0;
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input [0:5] rd_adr_0;
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input rd_enb_1;
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input [0:5] rd_adr_1;
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input wr_enb_0;
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input [0:5] wr_adr_0;
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// predecoded address signal
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// four groups of one hot encoded signals
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// read address 0
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output rd0_c_na0;
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output rd0_c_a0;
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output rd0_na1_na2;
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output rd0_na1_a2;
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output rd0_a1_na2;
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output rd0_a1_a2;
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output rd0_na3;
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output rd0_a3;
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output rd0_na4_na5;
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output rd0_na4_a5;
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output rd0_a4_na5;
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output rd0_a4_a5;
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// read address 1
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output rd1_c_na0;
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output rd1_c_a0;
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output rd1_na1_na2;
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output rd1_na1_a2;
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output rd1_a1_na2;
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output rd1_a1_a2;
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output rd1_na3;
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output rd1_a3;
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output rd1_na4_na5;
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output rd1_na4_a5;
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output rd1_a4_na5;
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output rd1_a4_a5;
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// write address 0
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output wr0_c_na0;
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output wr0_c_a0;
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output wr0_na1_na2;
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output wr0_na1_a2;
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output wr0_a1_na2;
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output wr0_a1_a2;
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output wr0_na3;
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output wr0_a3;
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output wr0_na4_na5;
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output wr0_na4_a5;
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output wr0_a4_na5;
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output wr0_a4_a5;
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// one predecoder per port
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predecode predecode_r0(
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.strobe(strobe),
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.enable(rd_enb_0),
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.address(rd_adr_0),
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.c_na0(rd0_c_na0),
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.c_a0(rd0_c_a0),
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.na1_na2(rd0_na1_na2),
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.na1_a2(rd0_na1_a2),
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.a1_na2(rd0_a1_na2),
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.a1_a2(rd0_a1_a2),
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.na3(rd0_na3),
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.a3(rd0_a3),
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.na4_na5(rd0_na4_na5),
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.na4_a5(rd0_na4_a5),
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.a4_na5(rd0_a4_na5),
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.a4_a5(rd0_a4_a5)
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);
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predecode predecode_r1(
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.strobe(strobe),
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.enable(rd_enb_1),
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.address(rd_adr_1),
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.c_na0(rd1_c_na0),
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.c_a0(rd1_c_a0),
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.na1_na2(rd1_na1_na2),
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.na1_a2(rd1_na1_a2),
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.a1_na2(rd1_a1_na2),
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.a1_a2(rd1_a1_a2),
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.na3(rd1_na3),
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.a3(rd1_a3),
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.na4_na5(rd1_na4_na5),
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.na4_a5(rd1_na4_a5),
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.a4_na5(rd1_a4_na5),
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.a4_a5(rd1_a4_a5)
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);
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predecode predecode_w0(
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.strobe(strobe),
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.enable(wr_enb_0),
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.address(wr_adr_0),
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.c_na0(wr0_c_na0),
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.c_a0(wr0_c_a0),
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.na1_na2(wr0_na1_na2),
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.na1_a2(wr0_na1_a2),
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.a1_na2(wr0_a1_na2),
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.a1_a2(wr0_a1_a2),
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.na3(wr0_na3),
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.a3(wr0_a3),
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.na4_na5(wr0_na4_na5),
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.na4_a5(wr0_na4_a5),
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.a4_na5(wr0_a4_na5),
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.a4_a5(wr0_a4_a5)
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);
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endmodule
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